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path: root/src/mesa/drivers/dri/i965/gen7_misc_state.c
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* intel: Make intel_region's pitch be bytes instead of pixels.Eric Anholt2013-01-181-3/+3
* i965: Move all the depth/stencil/hiz offset logic into the workaround.Eric Anholt2012-11-191-79/+11
* i965: Fix rendering to small mipmaps of depth/stencil buffers using a temp mt.Eric Anholt2012-10-161-60/+40
* i965: Share the draw x/y offset masking code between main/blorp and all gens.Eric Anholt2012-10-161-36/+5
* intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset.Paul Berry2012-09-121-2/+4
* intel: Add map_stencil_as_y_tiled to intel_region_get_tile_masks.Paul Berry2012-09-121-2/+3
* i965/gen6+: Add support for fast depth clears.Eric Anholt2012-05-231-2/+2
* i965/gen7: Set tile_x/y to 0 in the no-stencil case.Eric Anholt2012-05-141-1/+1
* i965/Gen7: Work around GPU hangs due to misaligned depth coordinate offsets.Paul Berry2012-05-071-0/+36
* i965: Fix mipmap offsets for HiZ and separate stencil buffers.Paul Berry2012-05-071-7/+72
* i965: Stop lying about cpp and height of a stencil buffer.Paul Berry2012-04-101-1/+15
* i965: Set "Stencil Buffer Enable" bit on Haswell.Kenneth Graunke2012-03-301-1/+4
* intel: derive intel_renderbuffer from swrast_renderbufferBrian Paul2012-01-241-4/+4
* i965/gen7: Fix depth buffer rendering to tile offsets.Eric Anholt2012-01-121-2/+2
* i965: Fix compiler warnings from hiz changes.Eric Anholt2012-01-101-2/+0
* i965/gen7: Fix batch length for 3DSTATE_HIER_DEPTH_BUFFERChad Versace2012-01-101-2/+2
* i965/gen7: Enable HiZChad Versace2012-01-101-8/+23
* i965: Replace references to stencil region size with buffer sizeChad Versace2012-01-101-2/+4
* i965: Properly demote the depth mt format for fake packed depth/stencil.Eric Anholt2011-12-191-0/+1
* intel: Stop creating the wrapped stencil irb.Eric Anholt2011-12-191-10/+22
* i965: Base HW depth format setup based on MESA_FORMAT, not bpp.Eric Anholt2011-11-291-29/+1
* intel: Replace intel_renderbuffer::region with a miptree [v3]Chad Versace2011-11-211-5/+6
* i965: Remove the validated BO list, now that it's unused.Eric Anholt2011-10-291-15/+0
* intel: Rename region->buffer to region->bo, and remove accessor function.Eric Anholt2011-09-261-4/+4
* i965: Emit depth stalls and flushes before changing depth state on Gen6+.Kenneth Graunke2011-09-261-0/+2
* intel: Move the draw_x/draw_y to the renderbuffer where it belongs.Eric Anholt2011-06-131-1/+1
* i965/gen7: Program stencil buffers on Ivybridge.Kenneth Graunke2011-06-081-19/+42
* i965/gen7: Add a prepare_depthbuffer function.Kenneth Graunke2011-06-081-0/+15
* i965/gen7: gen7_emit_depthbuffer needs the _NEW_DEPTH dirty bit.Kenneth Graunke2011-06-081-1/+2
* i965/gen7: Remove stencil renderbuffer from gen7_depth_format.Kenneth Graunke2011-06-081-3/+0
* i965/gen7: Add support for rendering to depthbuffer mipmap levels > 0.Kenneth Graunke2011-05-201-2/+6
* i965: Stop caching the combined depth/stencil region in brw_context.c.Eric Anholt2011-05-181-5/+23
* i965: Add depth buffer support on Ivybridge.Kenneth Graunke2011-05-171-0/+122
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