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path: root/src/mesa/drivers/dri/i965/brw_misc_state.c
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* i965/gen6: Simplify hiz surface setupTopi Pohjolainen2017-01-271-3/+2
* i965: Remove check for hiz on earlier gens than SNBTopi Pohjolainen2017-01-271-16/+2
* i965: Program 3DSTATE_AA_LINE_PARAMETERS in upload_invariant_stateNanley Chery2016-10-311-31/+10
* i965/miptree: Remove the stencil_as_y_tiled parameter from get_aligned_offsetJason Ekstrand2016-10-271-4/+2
* i965/miptree: Remove the stencil_as_y_tiled parameter from get_tile_masksJason Ekstrand2016-08-171-3/+3
* i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.Francisco Jerez2016-07-071-9/+0
* i965: Assert that a depth_mt exists when using HiZ.Matt Turner2016-05-251-0/+1
* i965: Send the minimal number of STATE_BASE_ADDRESS packets.Kenneth Graunke2016-05-161-9/+4
* i965: Combine Gen4-7 and Gen8+ state base address emitters.Kenneth Graunke2016-05-161-4/+42
* i965: Drop BRW_NEW_BLORP from stipple and line parameter packets.Kenneth Graunke2016-05-121-8/+4
* i965/blorp: Do not trigger re-emission of base state addressTopi Pohjolainen2016-04-231-1/+0
* i965: Make all atoms to track BRW_NEW_BLORP by defaultKenneth Graunke2016-04-231-7/+16
* i965: Rename define for the PIPE_CONTROL DC flush bit.Francisco Jerez2016-02-081-1/+1
* i965/gen7.5+: Disable resource streamer during GPGPU workloads.Francisco Jerez2016-01-141-0/+40
* i965/gen7: Emit stall and dummy primitive draw after switching to the 3D pipe...Francisco Jerez2016-01-141-0/+24
* i965/gen4-5: Emit MI_FLUSH as required prior to switching pipelines.Francisco Jerez2016-01-141-0/+13
* i965/gen6-7: Implement stall and flushes required prior to switching pipelines.Francisco Jerez2016-01-141-0/+37
* i965/gen8+: Invalidate color calc state when switching to the GPGPU pipeline.Francisco Jerez2016-01-141-0/+20
* i965: add EXT_polygon_offset_clamp support to gen4/gen5Ilia Mirkin2015-10-051-8/+0
* i965: Use intel_get_tile_dims() to get tile masksAnuj Phogat2015-09-281-7/+13
* i965: Always re-emit the pipeline select during invariant state emissionChris Wilson2015-08-241-1/+2
* i965: Trivial formatting changes in brw_misc_state.cIan Romanick2015-08-031-26/+23
* i965: Use float calculations when double is unnecessary.Matt Turner2015-07-291-2/+2
* i965: Rename intel_emit* to reflect their new location in brw_pipe_controlChris Wilson2015-06-241-1/+1
* i965: Use _mesa_geometric_ functions appropriatelyKevin Rogovin2015-06-171-3/+6
* i965/state: Emit pipeline select when changing pipelinesJordan Justen2015-05-021-6/+17
* i965/state: Don't use brw->state.dirty.brwJordan Justen2015-03-311-2/+2
* i965/hiz: Start to separate miptree out from hiz buffersJordan Justen2015-03-091-2/+2
* i965: Do Sandybridge workaround flushes before each primitive.Kenneth Graunke2015-02-171-27/+0
* i965: Delete brw_state_flags::cache and related code.Kenneth Graunke2014-12-021-8/+0
* i965: Move BRW_NEW_*_PROG_DATA flags to .brw (not .cache).Kenneth Graunke2014-12-021-1/+1
* i965: Rename CACHE_NEW_*_PROG to BRW_NEW_*_PROG_DATA.Kenneth Graunke2014-12-021-1/+1
* i965: Combine CACHE_NEW_*_UNIT into BRW_NEW_GEN4_UNIT_STATE.Kenneth Graunke2014-11-291-7/+2
* i965: Alphabetize brw_tracked_state flags and use a consistent style.Kenneth Graunke2014-11-291-16/+16
* i965: Always enable VF statisticsBen Widawsky2014-11-131-2/+1
* i965/skl: Set mask bits in PIPELINE_SELECT on Skylake.Kenneth Graunke2014-11-031-1/+1
* Revert 5 i965 patches: 8e27a4d2, 373143ed, c5bdf9be, 6f56e142, 88e3d404Jordan Justen2014-09-041-2/+2
* i965: Create a macro for setting a dirty bit.Paul Berry2014-09-011-2/+2
* i965/gen6 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surfaceJordan Justen2014-08-151-2/+2
* i965: Move has_hiz from the slice to the level.Eric Anholt2014-05-121-1/+1
* i965: Delete the intel_regions.c code.Eric Anholt2014-05-011-1/+0
* i965: Drop use of intel_region from miptrees.Eric Anholt2014-05-011-14/+12
* i965: Move intel_region_get_aligned_offset() to be a miptree function.Eric Anholt2014-05-011-9/+8
* i965: Move intel_region_get_tile_masks() to be a miptree function.Eric Anholt2014-05-011-7/+7
* i965: Actually emit PIPELINE_SELECT and 3DSTATE_VF_STATISTICS.Kenneth Graunke2014-05-011-2/+8
* i965: Fix render-to-texture in non-FinishRenderTexture cases.Eric Anholt2014-03-061-0/+5
* i965: Pull format conversion logic out of brw_depthbuffer_format.Kenneth Graunke2014-02-191-32/+1
* mesa: Fix MESA_FORMAT_Z24_UNORM_S8_UINT vs. X8_UINT mix-up.Kenneth Graunke2014-02-091-3/+3
* mesa: Change many Type P MESA_FORMATs to meet naming specMark Mueller2014-01-271-5/+5
* mesa: Change many Type A MESA_FORMATs to meet naming standardMark Mueller2014-01-271-5/+5
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