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authorJordan Justen <[email protected]>2013-07-09 15:36:32 -0700
committerJordan Justen <[email protected]>2014-08-15 20:11:41 -0700
commit56cdb55e38ca352a0d521d7aa69b46ffbd855192 (patch)
tree0faa1b033b16d702644e082a978e6ffa87314db2 /src/mesa/drivers/dri/i965/brw_misc_state.c
parent3da13aef012a7edd6d2b07452865812f072d4b01 (diff)
i965/gen6 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surface
(bf25ee2 for gen6) Previously we would always find the 2D sub-surface of interest, and then program the surface to this location. Now we always program the 3DSTATE_DEPTH_BUFFER at the start of the surface. To select the lod/slice, we utilize the lod & minimum array element fields. We also must disable brw_workaround_depthstencil_alignment for gen >= 6. Now the hardware will handle alignment when rendering to additional slices/LODs. v3: * Set depth_mt bo RELOC offset to 0, as was done in bf25ee2 Signed-off-by: Jordan Justen <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56127 Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_misc_state.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 76e22bd5ac9..e3980fc3408 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -261,10 +261,10 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw,
if (stencil_irb)
brw->depthstencil.stencil_mt = get_stencil_miptree(stencil_irb);
- /* Gen7+ doesn't require the workarounds, since we always program the
+ /* Gen6+ doesn't require the workarounds, since we always program the
* surface state at the start of the whole surface.
*/
- if (brw->gen >= 7)
+ if (brw->gen >= 6)
return;
/* Check if depth buffer is in depth/stencil format. If so, then it's only