diff options
| author | Francisco Jerez <[email protected]> | 2016-01-14 12:20:46 -0800 |
|---|---|---|
| committer | Francisco Jerez <[email protected]> | 2016-02-08 15:48:00 -0800 |
| commit | 53739fddc65a4cb34a2da14b873e95a451916267 (patch) | |
| tree | 579ddb9383b2602b25bee402eb0d8a9c336f88fb /src/mesa/drivers/dri/i965/brw_misc_state.c | |
| parent | 10d84ba9f084174a1e8e7639dfb05dd855ba86e8 (diff) | |
i965: Rename define for the PIPE_CONTROL DC flush bit.
Its previous name was somewhat misleading, this really behaves like a
RW cache flush rather than an invalidation.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_misc_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_misc_state.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 319c2a5669f..ab1a0d7255f 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -919,7 +919,7 @@ brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline) * MI_PIPELINE_SELECT command to change the Pipeline Select Mode. */ const unsigned dc_flush = - brw->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_INVALIDATE : 0; + brw->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0; if (brw->gen == 6) { /* Hardware workaround: SNB B-Spec says: |