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* intel/compiler: add and fix up fallthrough comments for gcc warningsTimothy Arceri2020-07-022-4/+4
* intel/compiler: Don't emit no-op cr0 changesMatt Turner2020-07-021-0/+3
* intel/compiler: Add assert that set bits are within maskMatt Turner2020-07-021-2/+5
* intel/eu: Add the RNDU opcodeJason Ekstrand2020-06-232-0/+2
* intel/eu: Set the right subnr for ALIGN16 destinationsJason Ekstrand2020-06-231-1/+1
* intel/eu: Add a brw_urb_dest_msg_type helperJason Ekstrand2020-06-231-0/+8
* intel/eu: Add a brw_urb_desc helperKenneth Graunke2020-06-231-0/+22
* intel/compiler: Expose brw_texture_offset to CJason Ekstrand2020-06-231-3/+3
* intel/fs: Move more prog_data setup into populate_wm_prog_dataJason Ekstrand2020-06-232-20/+20
* intel/fs: Break wm_prog_data setup into a helperJason Ekstrand2020-06-232-30/+43
* intel/fs: Expose a couple of NIR lowering helpersJason Ekstrand2020-06-232-6/+9
* intel/compiler: Always apply sample mask on Vulkan.Arcady Goldmints-Orlov2020-06-192-2/+3
* intel/compiler: Remove unnecessary optimization for MULSagar Ghuge2020-06-161-8/+0
* intel/compiler: Optimize integer add with 0 into movSagar Ghuge2020-06-161-0/+8
* intel/compiler: Drop opt_sampler_eot()Matt Turner2020-06-122-101/+0
* intel/nir: Call nir_metadata_preserve on !progressJason Ekstrand2020-06-115-6/+20
* nir: Call nir_metadata_preserve on !progressJason Ekstrand2020-06-111-0/+2
* intel/fs: Add Fall-through commentCaio Marcelo de Oliveira Filho2020-06-081-0/+1
* intel/compiler: Extract control barriers from scoped barriersBoris Brezillon2020-06-034-0/+87
* nir: Replace the scoped_memory barrier by a scoped_barrierBoris Brezillon2020-06-033-5/+8
* nir: add callback to nir_remove_dead_variables()Timothy Arceri2020-06-031-3/+3
* meson: use gnu_symbol_visibility argumentDylan Baker2020-06-011-2/+2
* intel/fs: Emit HALT for discard on Gen4-5Jason Ekstrand2020-05-306-30/+107
* intel/fs: Fix unused texture coordinate zeroing on Gen4-5Jason Ekstrand2020-05-301-1/+2
* intel/vec4: Stomp the return type of RESINFO to UINT32Jason Ekstrand2020-05-301-0/+11
* intel: Add helper to calculate GPGPU_WALKER::RightExecutionMaskCaio Marcelo de Oliveira Filho2020-05-271-0/+13
* intel/fs: Generate multiple CS SIMD variants for variable group sizeCaio Marcelo de Oliveira Filho2020-05-272-62/+163
* intel/fs: Add helper to get prog_offset and simd_sizeCaio Marcelo de Oliveira Filho2020-05-272-0/+22
* intel/fs: Support INTEL_DEBUG=no8,no32 in compute shadersCaio Marcelo de Oliveira Filho2020-05-271-2/+17
* intel/fs: Remove min_dispatch_width spilling decision from RACaio Marcelo de Oliveira Filho2020-05-272-38/+30
* intel/fs: Work around dual-source blending hangs in combination with SIMD16Danylo Piliaiev2020-05-271-2/+6
* intel: Use SATURATEAlyssa Rosenzweig2020-05-261-2/+2
* intel/fs: Remove redundant assert()Caio Marcelo de Oliveira Filho2020-05-261-3/+0
* intel/fs: Early return when can't satisfy explicit group sizeCaio Marcelo de Oliveira Filho2020-05-261-8/+11
* intel/fs: Remove unused state from brw_nir_lower_cs_intrinsicsCaio Marcelo de Oliveira Filho2020-05-261-16/+11
* intel/fs: Remove unused emission of load_simd_with_intelCaio Marcelo de Oliveira Filho2020-05-261-5/+0
* tree-wide: fix deprecated GitLab URLsEric Engestrom2020-05-231-1/+1
* i965/vec4: Ignore swizzle of VGRF for use by var_range_end()Andrii Simiklit2020-05-201-1/+1
* intel/fs: Use writes_memory from shader_infoCaio Marcelo de Oliveira Filho2020-05-182-25/+3
* intel/compiler: fix alignment assert in nir_emit_intrinsicArcady Goldmints-Orlov2020-05-121-1/+1
* nir: do not vectorize load/store if offset can overflow and robustness enabledSamuel Pitoiset2020-05-111-1/+2
* nir/algebraic: Split ibfe and ubfe with two constant sourcesIan Romanick2020-05-071-0/+1
* intel: Let drivers call brw_nir_lower_cs_intrinsics()Caio Marcelo de Oliveira Filho2020-05-011-2/+0
* intel/fs: Add and use a new load_simd_width_intel intrinsicCaio Marcelo de Oliveira Filho2020-05-014-34/+73
* intel/fs: Add an option to lower variable group size in backendCaio Marcelo de Oliveira Filho2020-05-012-1/+10
* intel/fs: Clean up variable group size handling in backendCaio Marcelo de Oliveira Filho2020-05-013-8/+4
* anv,iris: Fix input vertex max for tcs on gen12D Scott Phillips2020-05-011-1/+1
* intel/fs: Update location of Render Target Array Index for gen12D Scott Phillips2020-05-011-1/+9
* intel/eu: Use non-coherent mode (BTI=253) for stateless A64 messagesJason Ekstrand2020-04-302-10/+39
* intel/ir: Update performance analysis parameters for memory fence codegen cha...Francisco Jerez2020-04-291-4/+18
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