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path: root/src/mesa/drivers/dri/i965/gen7_misc_state.c
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* i965: drop brw->is_haswell in favor of devinfo->is_haswellLionel Landwerlin2017-08-301-1/+2
* i965: Reduce passing 2x32b of reloc_domains to 2 bitsChris Wilson2017-08-041-10/+3
* i965/miptree: Clean-up unusedTopi Pohjolainen2017-07-221-6/+2
* i965/miptree: Represent w-tiled stencil surfaces with islTopi Pohjolainen2017-07-201-2/+6
* i965/miptree: Switch to isl_surf::row_pitchTopi Pohjolainen2017-07-201-2/+2
* i965/miptree: Take interleaving into account in stencil pitchTopi Pohjolainen2017-07-201-11/+1
* mesa: replace _mesa_update_stencil() with helper functionsMarek Olšák2017-06-221-1/+1
* i965/miptree/gen7+: Use isl for hiz layoutsTopi Pohjolainen2017-06-191-3/+2
* i965/miptree: Store fast clear colors in an isl_color_valueJason Ekstrand2017-06-071-1/+6
* i965: Disable depth writes when depth test is GL_EQUAL.Kenneth Graunke2016-11-181-1/+1
* i965/miptree: Create a hiz mcs typeBen Widawsky2016-11-081-3/+3
* i965: Track that the stencil data was updated when renderingJordan Justen2016-08-261-0/+1
* i965: Assert that a depth_mt exists when using HiZ.Matt Turner2016-05-251-0/+1
* i965: Make all atoms to track BRW_NEW_BLORP by defaultKenneth Graunke2016-04-231-1/+2
* i965: Rename intel_emit* to reflect their new location in brw_pipe_controlChris Wilson2015-06-241-1/+1
* i965/gen7: Don't rely directly on the hiz miptree structureJordan Justen2015-03-091-3/+4
* i965/hiz: Start to separate miptree out from hiz buffersJordan Justen2015-03-091-1/+1
* i965: Delete brw_state_flags::cache and related code.Kenneth Graunke2014-12-021-1/+0
* i965: Alphabetize brw_tracked_state flags and use a consistent style.Kenneth Graunke2014-11-291-1/+3
* i965/gen7 depth: Set depth size based on LOD0 for 3D texturesJordan Justen2014-05-131-2/+2
* i965/Gen7: Set up layer constraints properly for depth buffersChris Forbes2014-05-091-9/+6
* i965: Delete the intel_regions.c code.Eric Anholt2014-05-011-1/+0
* i965: Drop use of intel_region from miptrees.Eric Anholt2014-05-011-6/+6
* i965/gen7: Skip repeated NULL depth/stencil state emits.Eric Anholt2014-04-111-0/+8
* i965: Fix clears of layered framebuffers with mismatched layer counts.Paul Berry2014-01-101-1/+1
* mesa: Track number of layers in layered framebuffers.Paul Berry2013-11-211-1/+1
* gen7: Use logical, not physical, dims in 3DSTATE_DEPTH_BUFFER (v2)Chad Versace2013-10-071-2/+2
* i965/gen7: Set MOCS L3 cacheability for IVB/BYT (v2)Ville Syrjälä2013-08-211-1/+1
* gen7 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surfaceJordan Justen2013-08-041-8/+28
* gen7 depth surface: calculate minimum array element being renderedJordan Justen2013-08-041-0/+10
* gen7 depth surface: calculate LOD being rendered toJordan Justen2013-08-041-0/+3
* gen7 depth surface: calculate depth (array size) for depth surfaceJordan Justen2013-08-041-0/+3
* gen7 depth surface: calculate more specific surface typeJordan Justen2013-08-041-0/+31
* i965/hsw: Change L3 MOCS for depth, hiz, and stencilChad Versace2013-07-181-2/+5
* i965: Cite the Sandybridge PRM for Gen7 stencil pitch requirements.Kenneth Graunke2013-07-151-9/+5
* i965: Delete intel_context entirely.Kenneth Graunke2013-07-091-2/+1
* i965: Move intel_context::is_<platform> flags to brw_context.Kenneth Graunke2013-07-091-1/+1
* i965: Pass brw_context to functions rather than intel_context.Kenneth Graunke2013-07-091-1/+1
* i965: Remove _NEW_DEPTH state flagging on drawbuffers change.Eric Anholt2013-06-251-1/+1
* intel: Replace checks for hiz_mt with intel_has*hiz()Chad Versace2013-04-101-5/+6
* i965: Fix stencil write enable flag in 3DSTATE_DEPTH_BUFFER on Gen7+.Kenneth Graunke2013-04-041-1/+1
* i965: Reduce code duplication in handling of depth, stencil, and HiZ.Paul Berry2013-04-021-62/+31
* intel: Make intel_region's pitch be bytes instead of pixels.Eric Anholt2013-01-181-3/+3
* i965: Move all the depth/stencil/hiz offset logic into the workaround.Eric Anholt2012-11-191-79/+11
* i965: Fix rendering to small mipmaps of depth/stencil buffers using a temp mt.Eric Anholt2012-10-161-60/+40
* i965: Share the draw x/y offset masking code between main/blorp and all gens.Eric Anholt2012-10-161-36/+5
* intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset.Paul Berry2012-09-121-2/+4
* intel: Add map_stencil_as_y_tiled to intel_region_get_tile_masks.Paul Berry2012-09-121-2/+3
* i965/gen6+: Add support for fast depth clears.Eric Anholt2012-05-231-2/+2
* i965/gen7: Set tile_x/y to 0 in the no-stencil case.Eric Anholt2012-05-141-1/+1
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