i965/miptree: Create a hiz mcs type

This seems counter to the goal of consolidating hiz, mcs, and later ccs buffers.
Unfortunately, hiz on gen6 is a thing the code supports, and this wart will be
helpful to achieve that. Overall, I believe it does help unify AUX buffers on
gen7+.

I updated the size field which I introduced in the previous patch, even though
we have no use for it.

XXX: As I mentioned in the last patch, the height given to the MCS buffer
allocation in intel_miptree_alloc_mcs() looks wrong, but I don't claim to fully
understand how the MCS buffer is laid out.

v2: rebase on master (Lionel)

Signed-off-by: Ben Widawsky <[email protected]> (v1)
Signed-off-by: Lionel Landwerlin <[email protected]> (v2)
Reviewed-by: Topi Pohjolainen <[email protected]>

1 files changed, 3 insertions, 3 deletions

diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 271d96230b7..7bd5cd5c053 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -146,13 +146,13 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
       ADVANCE_BATCH();
    } else {
       assert(depth_mt);
-      struct intel_miptree_aux_buffer *hiz_buf = depth_mt->hiz_buf;
+      struct intel_miptree_hiz_buffer *hiz_buf = depth_mt->hiz_buf;
 
       BEGIN_BATCH(3);
       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
       OUT_BATCH((mocs << 25) |
-                (hiz_buf->pitch - 1));
-      OUT_RELOC(hiz_buf->bo,
+                (hiz_buf->aux_base.pitch - 1));
+      OUT_RELOC(hiz_buf->aux_base.bo,
                 I915_GEM_DOMAIN_RENDER,
                 I915_GEM_DOMAIN_RENDER,
                 0);