index
:
mesa.git
gallium_va_encpackedheader01
master
Unnamed repository; edit this file 'description' to name the repository.
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
src
/
mesa
/
drivers
/
dri
/
i965
/
gen7_blorp.cpp
Commit message (
Expand
)
Author
Age
Files
Lines
*
i965: Move intel_context::batch to brw_context.
Kenneth Graunke
2013-07-09
1
-1
/
+1
*
i965: Pass brw_context to functions rather than intel_context.
Kenneth Graunke
2013-07-09
1
-43
/
+3
*
i965/blorp: Write blorp code to do render target resolves.
Paul Berry
2013-06-12
1
-0
/
+3
*
i965/gen7+: Implement fast color clear operation in BLORP.
Paul Berry
2013-06-12
1
-4
/
+14
*
i965/gen7+: Set up MCS in SURFACE_STATE whenever MCS is present.
Paul Berry
2013-06-12
1
-1
/
+1
*
i965/gen7+: Create an enum for keeping track of fast color clear state.
Paul Berry
2013-06-12
1
-0
/
+1
*
i965: Allocate push constant L3 space once at startup on Gen7+.
Kenneth Graunke
2013-06-10
1
-1
/
+0
*
i965: Disable pixel statistics in BLORP.
Kenneth Graunke
2013-05-20
1
-1
/
+0
*
i965: Fix hangs on HSW since the gen6 blorp fix.
Eric Anholt
2013-05-08
1
-2
/
+101
*
i965: Implement color clears using a simple shader in blorp.
Eric Anholt
2013-04-30
1
-5
/
+7
*
i965: Don't flush the batch at the end of blorp.
Eric Anholt
2013-04-30
1
-9
/
+0
*
i965/blorp: Remove unnecessary test in gen7_blorp_emit_depth_stencil_config.
Paul Berry
2013-04-10
1
-7
/
+5
*
i965: Change signature of brw_get_depthstencil_tile_masks()
Chad Versace
2013-04-10
1
-1
/
+4
*
intel: Hook up the WARN_ONCE macro to GL_ARB_debug_output.
Eric Anholt
2013-03-05
1
-0
/
+1
*
i965: add support for sample mask on Gen6+
Chris Forbes
2013-03-02
1
-1
/
+1
*
i965: Add WARN_ONCE for depthstencil workarounds we shouldn't be hitting.
Eric Anholt
2013-03-01
1
-0
/
+3
*
intel: Make intel_region's pitch be bytes instead of pixels.
Eric Anholt
2013-01-18
1
-5
/
+3
*
i965: Replace structs with bit-shifting for Gen7 SURFACE_STATE entries.
Kenneth Graunke
2013-01-03
1
-32
/
+33
*
i965: Share the draw x/y offset masking code between main/blorp and all gens.
Eric Anholt
2012-10-16
1
-1
/
+4
*
intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset.
Paul Berry
2012-09-12
1
-2
/
+2
*
i965/blorp: Account for offsets when emitting SURFACE_STATE.
Paul Berry
2012-09-12
1
-1
/
+11
*
i965/blorp: store x and y offsets in brw_blorp_mip_info.
Paul Berry
2012-09-12
1
-5
/
+3
*
i965/blorp: store surface width/height in brw_blorp_mip_info.
Paul Berry
2012-09-12
1
-11
/
+4
*
i965/blorp: Clarify why width/height must be adjusted for Gen6 IMS surfaces.
Paul Berry
2012-09-12
1
-0
/
+5
*
i965/msaa: Treat GL_SAMPLES=1 as equivalent to GL_SAMPLES=0.
Paul Berry
2012-08-01
1
-2
/
+2
*
i965: Fix typo in shader channel select field name.
Kenneth Graunke
2012-07-27
1
-4
/
+4
*
i965/blorp: Configure SURFACE_STATE correctly for IMS surfaces.
Paul Berry
2012-07-20
1
-1
/
+1
*
i965/msaa: Set SURFACE_STATE properly when CMS MSAA is in use.
Paul Berry
2012-07-11
1
-0
/
+4
*
i965/msaa: Implement glSampleCoverage.
Paul Berry
2012-06-26
1
-1
/
+1
*
i965/blorp: Refactor surface format determination.
Paul Berry
2012-06-07
1
-5
/
+1
*
i965/msaa: Modify blorp code to account for Gen7 MSAA layouts.
Paul Berry
2012-05-25
1
-4
/
+0
*
i965/msaa: Validate Gen7 surface state constraints.
Paul Berry
2012-05-25
1
-3
/
+8
*
i965/msaa: Properly handle sliced layout for Gen7.
Paul Berry
2012-05-25
1
-0
/
+2
*
i965/blorp: Enable blorp blits on Gen7.
Paul Berry
2012-05-25
1
-0
/
+2
*
i965/blorp: Use 16 pixel dispatch on Gen7.
Paul Berry
2012-05-25
1
-1
/
+9
*
i965/blorp: Allocate space for push constants on Gen7.
Paul Berry
2012-05-25
1
-23
/
+4
*
i965/blorp: Factor gen6_blorp_emit_batch_head into separate functions.
Paul Berry
2012-05-25
1
-0
/
+3
*
i965/blorp: Use MSDISPMODE_PERSAMPLE rendering when necessary
Paul Berry
2012-05-25
1
-3
/
+7
*
i965/gen6+: Add support for fast depth clears.
Eric Anholt
2012-05-23
1
-3
/
+2
*
i965/gen7: Add CC viewport setup to blorp code.
Eric Anholt
2012-05-23
1
-0
/
+21
*
i965: Drop a layer of indirection in doing HiZ resolves.
Eric Anholt
2012-05-23
1
-22
/
+0
*
i965/gen6: Initial implementation of MSAA.
Paul Berry
2012-05-15
1
-3
/
+17
*
i965/gen6+: Add code to perform blits on the render path ("blorp").
Paul Berry
2012-05-15
1
-7
/
+304
*
i965: split gen{6,7}_blorp_exec functions into manageable chunks.
Paul Berry
2012-05-15
1
-269
/
+281
*
i965: Parameterize HiZ code to prepare for adding blitting.
Paul Berry
2012-05-15
1
-52
/
+35
*
i965/hiz: Convert gen{6,7}_hiz.h to gen{6,7}_blorp.h
Paul Berry
2012-05-10
1
-2
/
+2
*
i965/hiz: Convert gen{6,7}_hiz.c to C++
Paul Berry
2012-05-10
1
-0
/
+501