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path: root/src/mesa/drivers/dri/i965/brw_state_upload.c
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* i965: Upload atomic buffer state for compute shadersJordan Justen2015-05-021-0/+2
* i965/state: Emit pipeline select when changing pipelinesJordan Justen2015-05-021-0/+5
* i965/cs: Emit state base addressJordan Justen2015-05-021-0/+2
* i965/cs: Upload brw_cs_stateJordan Justen2015-05-021-0/+2
* i965/cs: Emit compute shader code and upload programsJordan Justen2015-05-021-0/+3
* i965/cs: Add BRW_NEW_CS_PROG_DATA and BRW_CACHE_CS_PROGJordan Justen2015-05-021-0/+1
* i965/cs: Add BRW_NEW_COMPUTE_PROGRAM state flag.Paul Berry2015-05-021-0/+6
* i965/state: Remove brw->state.dirtyJordan Justen2015-03-311-6/+0
* i965/state: Don't use brw->state.dirty.mesaJordan Justen2015-03-311-7/+6
* i965/state: Don't use brw->state.dirty.brwJordan Justen2015-03-311-14/+13
* i965/state: Add compute pipeline with empty atom listsJordan Justen2015-03-311-1/+33
* i965/state: Only upload render programs for render state uploadsJordan Justen2015-03-311-20/+25
* i965/state: Create separate dirty state bits for each pipelineJordan Justen2015-03-311-27/+74
* i965/state: Support multiple pipelines in brw->num_atomsJordan Justen2015-03-311-37/+57
* i965/state: Rename brw_clear_dirty_bits to brw_render_state_finishedJordan Justen2015-03-311-1/+1
* i965/state: Rename brw_upload_state to brw_upload_render_stateJordan Justen2015-03-311-6/+6
* i965/skl: Disable partial resolve in VCBen Widawsky2015-03-271-0/+10
* i965: Perform program state upload outside of atom handlingCarl Worth2015-02-231-16/+19
* i965: Do Sandybridge workaround flushes before each primitive.Kenneth Graunke2015-02-171-0/+7
* i965: Store the atoms directly in the contextIan Romanick2015-01-141-3/+16
* i965: Make INTEL_DEBUG=state ignore state flags with a count of 1.Kenneth Graunke2015-01-031-2/+4
* i965: Compute VS attribute WA bits earlier and check if they changed.Kenneth Graunke2014-12-041-0/+1
* i965: Delete brw_state_flags::cache and related code.Kenneth Graunke2014-12-021-17/+3
* i965: Move BRW_NEW_*_PROG_DATA flags to .brw (not .cache).Kenneth Graunke2014-12-021-8/+7
* i965: Rename CACHE_NEW_*_PROG to BRW_NEW_*_PROG_DATA.Kenneth Graunke2014-12-021-7/+7
* i965: Move CACHE_NEW_SAMPLER to BRW_NEW_SAMPLER_STATE_TABLE.Kenneth Graunke2014-11-291-1/+1
* i965: Move CACHE_NEW_*_VP flags to BRW_NEW_*_VP.Kenneth Graunke2014-11-291-3/+3
* i965: Fold the gen7_cc_viewport_state_pointer atom into brw_cc_vp.Kenneth Graunke2014-11-291-2/+0
* i965: Combine CACHE_NEW_*_UNIT into BRW_NEW_GEN4_UNIT_STATE.Kenneth Graunke2014-11-291-6/+1
* i965: Implement the PMA stall fix.Kenneth Graunke2014-11-041-0/+6
* i965: Have mesa flag BRW_NEW_TEXTURE_BUFFER when a TexBO binding changesChris Forbes2014-10-161-0/+1
* i965: Add new dirty flag for new TexBOs.Chris Forbes2014-10-161-0/+1
* i965: Use ~0ull when flagging all BRW_NEW_* dirty flags.Kenneth Graunke2014-10-011-2/+2
* i965: Fix INTEL_DEBUG=state to work with 64-bit dirty bits.Kenneth Graunke2014-10-011-16/+7
* i965: Delete CACHE_NEW_BLORP_CONST_COLOR_PROG.Kenneth Graunke2014-10-011-1/+0
* i965/gen6/gs: upload ubo and pull constants surfaces.Iago Toral Quiroga2014-09-191-0/+2
* i965/gen6/gs: Enable texture units and upload sampler state.Iago Toral Quiroga2014-09-191-0/+1
* i965/gs: Reuse gen6 constant push buffers setup code in gen7+.Samuel Iglesias Gonsalvez2014-09-191-2/+2
* i965/gen6/gs: Setup constant push buffers for gen6 geometry shaders.Iago Toral Quiroga2014-09-191-0/+1
* i965/gen6/gs: use brw_gs_prog atom instead of brw_ff_gs_progSamuel Iglesias Gonsalvez2014-09-191-1/+1
* i965: Calculate start/base_vertex_location after preparing vertices.Kenneth Graunke2014-09-101-3/+3
* Revert 5 i965 patches: 8e27a4d2, 373143ed, c5bdf9be, 6f56e142, 88e3d404Jordan Justen2014-09-041-48/+37
* mesa: Convert NewDriverState to 64-bitsJordan Justen2014-09-011-1/+1
* i965: Modify state upload to allow 2 different sets of state atoms.Paul Berry2014-09-011-23/+30
* i965: Modify dirty bit handling to support 2 pipelines.Paul Berry2014-09-011-5/+9
* i965: Create a macro for setting all dirty bits.Paul Berry2014-09-011-2/+2
* i965: Create a macro for setting a dirty bit.Paul Berry2014-09-011-7/+7
* i965: Track the number of samples in the drawbuffer.Eric Anholt2014-04-301-0/+6
* i965: Drop intel_check_front_buffer_rendering().Eric Anholt2014-03-111-2/+0
* i965: Update GS state for Broadwell.Kenneth Graunke2014-01-311-1/+1
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