diff options
| author | Kenneth Graunke <[email protected]> | 2015-01-09 23:07:56 -0800 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2015-02-17 15:24:14 -0800 |
| commit | 0b499abb51c80867ad034f2a6d9fcb1e86d021cc (patch) | |
| tree | 6a8a351443a4f7b1883aaa82dda1294832fab1d4 /src/mesa/drivers/dri/i965/brw_state_upload.c | |
| parent | 92163482bda87216764edc0beca3ca090678038d (diff) | |
i965: Do Sandybridge workaround flushes before each primitive.
Sandybridge requires the post-sync non-zero workaround in a ton of
places, and if you ever miss one, the GPU usually hangs.
Currently, we try to track exactly when a workaround flush is
necessary (via the brw->batch.need_workaround_flush flag). This is
tricky to get right, and we've botched it several times in the past.
This patch unconditionally performs the post-sync non-zero flush at the
start of each primitive's state upload (including BLORP). We drop the
needs_workaround_flush flag, and drop all the other callers, as the
flush has already been performed.
We have no data to indicate that simply flushing all the time will
hurt performance, and it has the potential to help stability.
v2: Add post-sync workaround to initial GPU state upload to be extra
cautious (suggested by Chad Versace).
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Chad Versace <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_state_upload.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 52d96f40413..84e5c104bf3 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -344,6 +344,9 @@ brw_upload_initial_gpu_state(struct brw_context *brw) if (!brw->hw_ctx) return; + if (brw->gen == 6) + intel_emit_post_sync_nonzero_flush(brw); + brw_upload_invariant_state(brw); if (brw->gen >= 8) { @@ -612,6 +615,10 @@ void brw_upload_state(struct brw_context *brw) if ((state->mesa | state->brw) == 0) return; + /* Emit Sandybridge workaround flushes on every primitive, for safety. */ + if (brw->gen == 6) + intel_emit_post_sync_nonzero_flush(brw); + if (unlikely(INTEL_DEBUG)) { /* Debug version which enforces various sanity checks on the * state flags which are generated and checked to help ensure |