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path: root/src/mesa/drivers/dri/i965/brw_misc_state.c
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* intel: Apply Geminilake "Barrier Mode" workaround.Kenneth Graunke2018-01-091-0/+15
* i965: Reorganize batch/state BO fields into a 'brw_growing_bo' struct.Kenneth Graunke2017-11-291-12/+12
* i965: Program the dynamic state heap size to MAX_STATE_SIZE.Kenneth Graunke2017-11-291-1/+1
* i965: Upload invariant state once at the start of the batch on Gen4-5.Kenneth Graunke2017-11-161-9/+0
* i965: Add more precise cache tracking helpersJason Ekstrand2017-11-131-2/+2
* i965: Use a separate state buffer, but avoid changing flushing behavior.Kenneth Graunke2017-09-141-13/+13
* i965: drop brw->has_surface_tile_offset in favor of devinfo'sLionel Landwerlin2017-08-301-1/+2
* i965: drop brw->is_haswell in favor of devinfo->is_haswellLionel Landwerlin2017-08-301-1/+1
* i965: drop brw->is_g4x in favor of devinfo->is_g4xLionel Landwerlin2017-08-301-4/+4
* i965: drop brw->gen in favor of devinfo->genLionel Landwerlin2017-08-301-27/+36
* i965: Reduce passing 2x32b of reloc_domains to 2 bitsChris Wilson2017-08-041-33/+18
* i965: Drop redundant check for non-tiled depth bufferTopi Pohjolainen2017-07-201-2/+1
* i965/miptree: Switch to isl_surf::row_pitchTopi Pohjolainen2017-07-201-1/+1
* i965/miptree: Switch to isl_surf::tilingTopi Pohjolainen2017-07-201-4/+4
* i965/gen4: Set tile offsets to zero after depth rebaseTopi Pohjolainen2017-07-181-4/+6
* i965/gen4: Add support for single layer in alignment workaroundTopi Pohjolainen2017-06-191-2/+2
* i965/gen4: Refactor depth/stencil rebaseTopi Pohjolainen2017-06-181-180/+63
* i965: Drop depth/stencil miptree pointers in alignment workaroundTopi Pohjolainen2017-06-181-12/+3
* i965/gen4: Simplify depth/stencil invalidate checkTopi Pohjolainen2017-06-181-13/+3
* i965/gen4: Remove redundant check for depth when rebasing stencilTopi Pohjolainen2017-06-181-51/+12
* i965/gen4: Remove non-existing stencil and hiz buffer setupTopi Pohjolainen2017-06-181-115/+10
* i965/gen4: Set depth offset when there is stencil attachment onlyTopi Pohjolainen2017-06-171-0/+6
* i965: Do an end-of-pipe sync prior to STATE_BASE_ADDRESSJason Ekstrand2017-06-141-6/+12
* i965: Flush around state base addressJason Ekstrand2017-06-141-0/+32
* i965/miptree: Store fast clear colors in an isl_color_valueJason Ekstrand2017-06-071-1/+22
* i965: Port gen4+ state emitting code to genxml.Rafael Antognolli2017-05-031-147/+0
* i965: Delete tile resource mode codeAnuj Phogat2017-03-271-2/+1
* i965/gen8+: Do full stall when switching pipelineTopi Pohjolainen2017-03-161-1/+2
* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-131-1/+1
* i965: split EU defines to brw_eu_defines.hEmil Velikov2017-03-131-0/+1
* i965: Delete vestiges of resource streamer code.Kenneth Graunke2017-03-061-40/+0
* i965/gen6: Simplify hiz surface setupTopi Pohjolainen2017-01-271-3/+2
* i965: Remove check for hiz on earlier gens than SNBTopi Pohjolainen2017-01-271-16/+2
* i965: Program 3DSTATE_AA_LINE_PARAMETERS in upload_invariant_stateNanley Chery2016-10-311-31/+10
* i965/miptree: Remove the stencil_as_y_tiled parameter from get_aligned_offsetJason Ekstrand2016-10-271-4/+2
* i965/miptree: Remove the stencil_as_y_tiled parameter from get_tile_masksJason Ekstrand2016-08-171-3/+3
* i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.Francisco Jerez2016-07-071-9/+0
* i965: Assert that a depth_mt exists when using HiZ.Matt Turner2016-05-251-0/+1
* i965: Send the minimal number of STATE_BASE_ADDRESS packets.Kenneth Graunke2016-05-161-9/+4
* i965: Combine Gen4-7 and Gen8+ state base address emitters.Kenneth Graunke2016-05-161-4/+42
* i965: Drop BRW_NEW_BLORP from stipple and line parameter packets.Kenneth Graunke2016-05-121-8/+4
* i965/blorp: Do not trigger re-emission of base state addressTopi Pohjolainen2016-04-231-1/+0
* i965: Make all atoms to track BRW_NEW_BLORP by defaultKenneth Graunke2016-04-231-7/+16
* i965: Rename define for the PIPE_CONTROL DC flush bit.Francisco Jerez2016-02-081-1/+1
* i965/gen7.5+: Disable resource streamer during GPGPU workloads.Francisco Jerez2016-01-141-0/+40
* i965/gen7: Emit stall and dummy primitive draw after switching to the 3D pipe...Francisco Jerez2016-01-141-0/+24
* i965/gen4-5: Emit MI_FLUSH as required prior to switching pipelines.Francisco Jerez2016-01-141-0/+13
* i965/gen6-7: Implement stall and flushes required prior to switching pipelines.Francisco Jerez2016-01-141-0/+37
* i965/gen8+: Invalidate color calc state when switching to the GPGPU pipeline.Francisco Jerez2016-01-141-0/+20
* i965: add EXT_polygon_offset_clamp support to gen4/gen5Ilia Mirkin2015-10-051-8/+0
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