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path: root/src/mesa/drivers/dri/i965/brw_context.h
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* i965: Setup pull constant state for compute programsJordan Justen2015-11-011-1/+1
* i965: remove cache_aux_free_func arrayEmil Velikov2015-10-281-5/+0
* glsl: keep track of intra-stage indices for atomicsTimothy Arceri2015-10-271-1/+1
* i965/vec4: print predicate control at brw_vec4 dump_instructionAlejandro Piñeiro2015-10-221-0/+1
* i965: Move the entire compiler API into a single fileJason Ekstrand2015-10-191-355/+1
* i965: Adapt SSBOs to work with their own separate index spaceIago Toral Quiroga2015-10-141-3/+1
* i965/gs: Make MAX_GS_INPUT_VERTICES a #define in brw_context.h.Kenneth Graunke2015-10-101-0/+2
* i965/vs: Unify URB entry size/read length calculations between backends.Kenneth Graunke2015-10-101-0/+2
* i965: Use util_next_power_of_two() for brw_get_scratch_size()Kristian Høgsberg Kristensen2015-10-081-1/+6
* i965/cs: Split out helper for building local id payloadKristian Høgsberg Kristensen2015-10-081-0/+1
* i965: add EXT_polygon_offset_clamp support to gen4/gen5Ilia Mirkin2015-10-051-0/+2
* i965: Assert on the number of combined UBO and SSBO binding table entriesIago Toral Quiroga2015-10-051-0/+3
* i965: Reserve binding table space for SSBO surfacesIago Toral Quiroga2015-10-051-0/+1
* i965: Define BRW_MAX_SSBOIago Toral Quiroga2015-10-051-0/+3
* i965: Define BRW_MAX_UBOIago Toral Quiroga2015-10-051-1/+4
* i965/cs: Upload UBO/SSBO surfacesJordan Justen2015-09-301-1/+1
* i965: Get rid of prog_data compare functionsJason Ekstrand2015-09-301-26/+1
* i965/state_cache: Remove the aux_compare fieldsJason Ekstrand2015-09-301-7/+0
* i965/cs: Setup surface binding for gl_NumWorkGroupsJordan Justen2015-09-291-1/+4
* i965/cs: Add a binding table entry for gl_NumWorkGroupsJordan Justen2015-09-291-1/+10
* i965/cs: Store compute invocation information in brw contextJordan Justen2015-09-291-0/+11
* i965: Implement "Static Vertex Count" geometry shader optimization.Kenneth Graunke2015-09-261-0/+5
* i965: Simplify handling of VUE map changes.Kenneth Graunke2015-09-261-11/+1
* i965: Don't re-layout varyings for separate shader programs.Kenneth Graunke2015-09-261-1/+13
* i965: Upload Shader Storage Buffer Object surfacesIago Toral Quiroga2015-09-251-0/+6
* i965/cs: Enable barrier in MEDIA_INTERFACE_DESCRIPTORJordan Justen2015-09-101-0/+1
* i965/cs: Emit texture surfaces to enable CS samplingJordan Justen2015-09-101-1/+1
* i965: Remove legacy clip plane handling from geometry shaders.Kenneth Graunke2015-09-031-5/+0
* i965/cs: Setup push constant data for uniformsJordan Justen2015-09-021-1/+1
* i965/gen7-8: Set up early depth/stencil control appropriately for image load/...Francisco Jerez2015-08-111-0/+1
* i965: Hook up image state upload.Francisco Jerez2015-08-111-2/+8
* i965: Define and initialize image parameter structure.Francisco Jerez2015-08-111-0/+54
* i965: Implement surface state set-up for shader images.Francisco Jerez2015-08-111-0/+2
* i965: Change the type of max_{vs, hs, ...}_threads variables to unsignedAnuj Phogat2015-07-291-6/+6
* i965: Enable hardware-generated binding tables on render path.Abdiel Janulgue2015-07-181-0/+6
* i965: Enable resource streamer for the batchbufferAbdiel Janulgue2015-07-181-0/+1
* i965: Optimize batchbuffer macros.Matt Turner2015-07-151-2/+3
* i965: Set brw->batch.emit only #ifdef DEBUG.Matt Turner2015-07-091-0/+2
* i965: Move pipecontrol workaround bo to brw_pipe_controlChris Wilson2015-07-081-4/+8
* i965/skl: Set the pulls bary bit in 3DSTATE_PS_EXTRANeil Roberts2015-07-061-0/+1
* i965/bxt: Add basic Broxton infrastructureBen Widawsky2015-06-241-0/+1
* i965: Rename intel_emit* to reflect their new location in brw_pipe_controlChris Wilson2015-06-241-3/+3
* i965: Transplant PIPE_CONTROL routines to brw_pipe_controlChris Wilson2015-06-241-0/+11
* i965: Use a single index per shader for shader_time.Jason Ekstrand2015-06-231-11/+3
* i965: Add compiler options to brw_compilerJason Ekstrand2015-06-231-1/+0
* i965: Rename use_linear_1d_layout() and make it globalAnuj Phogat2015-06-161-0/+4
* i965: Create a shader_dispatch_mode enum to replace VS/GS fields.Kenneth Graunke2015-06-011-9/+7
* i965: Add Gen9 surface state decodingBen Widawsky2015-05-181-0/+1
* i965: Use predicate enable bit for conditional rendering w/o stallingNeil Roberts2015-05-121-0/+23
* i956: Add a function to load a 64-bit register from a bufferNeil Roberts2015-05-121-0/+5
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