diff options
| author | Chris Wilson <[email protected]> | 2015-04-30 16:53:12 +0100 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2015-06-24 10:35:04 -0700 |
| commit | 9d4b9f1e0c661e5ed8ce2e71c76ce8cc1adf90dd (patch) | |
| tree | ff61570a0c304a4fbfe76b1e0f174b09883026e3 /src/mesa/drivers/dri/i965/brw_context.h | |
| parent | 147cdb53ecd225ea21d8d552607d384217346ecb (diff) | |
i965: Transplant PIPE_CONTROL routines to brw_pipe_control
Start trimming the fat from intel_batchbuffer.c. First by moving the set
of routines for emitting PIPE_CONTROLS (along with the lore concerning
hardware workarounds) to a separate brw_pipe_control.c
Signed-off-by: Chris Wilson <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_context.h')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index a7d83f8d7b4..761110beef3 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1998,6 +1998,17 @@ bool gen9_use_linear_1d_layout(const struct brw_context *brw, const struct intel_mipmap_tree *mt); +/* brw_pipe_control.c */ +void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags); +void brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags, + drm_intel_bo *bo, uint32_t offset, + uint32_t imm_lower, uint32_t imm_upper); +void intel_batchbuffer_emit_mi_flush(struct brw_context *brw); +void intel_emit_post_sync_nonzero_flush(struct brw_context *brw); +void intel_emit_depth_stall_flushes(struct brw_context *brw); +void gen7_emit_vs_workaround_flush(struct brw_context *brw); +void gen7_emit_cs_stall_flush(struct brw_context *brw); + #ifdef __cplusplus } #endif |