aboutsummaryrefslogtreecommitdiffstats
path: root/src/intel/compiler
Commit message (Expand)AuthorAgeFilesLines
* intel/compiler: Extract control barriers from scoped barriersBoris Brezillon2020-06-034-0/+87
* nir: Replace the scoped_memory barrier by a scoped_barrierBoris Brezillon2020-06-033-5/+8
* nir: add callback to nir_remove_dead_variables()Timothy Arceri2020-06-031-3/+3
* meson: use gnu_symbol_visibility argumentDylan Baker2020-06-011-2/+2
* intel/fs: Emit HALT for discard on Gen4-5Jason Ekstrand2020-05-306-30/+107
* intel/fs: Fix unused texture coordinate zeroing on Gen4-5Jason Ekstrand2020-05-301-1/+2
* intel/vec4: Stomp the return type of RESINFO to UINT32Jason Ekstrand2020-05-301-0/+11
* intel: Add helper to calculate GPGPU_WALKER::RightExecutionMaskCaio Marcelo de Oliveira Filho2020-05-271-0/+13
* intel/fs: Generate multiple CS SIMD variants for variable group sizeCaio Marcelo de Oliveira Filho2020-05-272-62/+163
* intel/fs: Add helper to get prog_offset and simd_sizeCaio Marcelo de Oliveira Filho2020-05-272-0/+22
* intel/fs: Support INTEL_DEBUG=no8,no32 in compute shadersCaio Marcelo de Oliveira Filho2020-05-271-2/+17
* intel/fs: Remove min_dispatch_width spilling decision from RACaio Marcelo de Oliveira Filho2020-05-272-38/+30
* intel/fs: Work around dual-source blending hangs in combination with SIMD16Danylo Piliaiev2020-05-271-2/+6
* intel: Use SATURATEAlyssa Rosenzweig2020-05-261-2/+2
* intel/fs: Remove redundant assert()Caio Marcelo de Oliveira Filho2020-05-261-3/+0
* intel/fs: Early return when can't satisfy explicit group sizeCaio Marcelo de Oliveira Filho2020-05-261-8/+11
* intel/fs: Remove unused state from brw_nir_lower_cs_intrinsicsCaio Marcelo de Oliveira Filho2020-05-261-16/+11
* intel/fs: Remove unused emission of load_simd_with_intelCaio Marcelo de Oliveira Filho2020-05-261-5/+0
* tree-wide: fix deprecated GitLab URLsEric Engestrom2020-05-231-1/+1
* i965/vec4: Ignore swizzle of VGRF for use by var_range_end()Andrii Simiklit2020-05-201-1/+1
* intel/fs: Use writes_memory from shader_infoCaio Marcelo de Oliveira Filho2020-05-182-25/+3
* intel/compiler: fix alignment assert in nir_emit_intrinsicArcady Goldmints-Orlov2020-05-121-1/+1
* nir: do not vectorize load/store if offset can overflow and robustness enabledSamuel Pitoiset2020-05-111-1/+2
* nir/algebraic: Split ibfe and ubfe with two constant sourcesIan Romanick2020-05-071-0/+1
* intel: Let drivers call brw_nir_lower_cs_intrinsics()Caio Marcelo de Oliveira Filho2020-05-011-2/+0
* intel/fs: Add and use a new load_simd_width_intel intrinsicCaio Marcelo de Oliveira Filho2020-05-014-34/+73
* intel/fs: Add an option to lower variable group size in backendCaio Marcelo de Oliveira Filho2020-05-012-1/+10
* intel/fs: Clean up variable group size handling in backendCaio Marcelo de Oliveira Filho2020-05-013-8/+4
* anv,iris: Fix input vertex max for tcs on gen12D Scott Phillips2020-05-011-1/+1
* intel/fs: Update location of Render Target Array Index for gen12D Scott Phillips2020-05-011-1/+9
* intel/eu: Use non-coherent mode (BTI=253) for stateless A64 messagesJason Ekstrand2020-04-302-10/+39
* intel/ir: Update performance analysis parameters for memory fence codegen cha...Francisco Jerez2020-04-291-4/+18
* intel/fs: Don't delete coalesced MOVs if they have a cmodJason Ekstrand2020-04-291-2/+15
* intel/fs: Only stall after sending all memory fence messagesCaio Marcelo de Oliveira Filho2020-04-291-19/+16
* intel/fs,vec4: Pull stall logic for memory fences up into the IRCaio Marcelo de Oliveira Filho2020-04-297-109/+118
* intel/fs: Allow FS_OPCODE_SCHEDULING_FENCE stall on registersCaio Marcelo de Oliveira Filho2020-04-292-2/+30
* intel/ir: Remove scheduling-based cycle count estimates.Francisco Jerez2020-04-283-26/+1
* intel/ir: Pass block cycle count information explicitly to disassembler.Francisco Jerez2020-04-285-6/+11
* intel/ir: Use brw::performance object instead of CFG cycle counts for codegen...Francisco Jerez2020-04-289-22/+45
* intel/fs: Add INTEL_DEBUG=no32 debugging flag.Francisco Jerez2020-04-281-1/+2
* intel/fs: Implement performance analysis-based SIMD32 heuristic for fragment ...Francisco Jerez2020-04-281-7/+17
* intel/fs: Heap-allocate fs_visitors in brw_compile_fs().Francisco Jerez2020-04-281-38/+39
* intel/ir: Import shader performance analysis pass.Francisco Jerez2020-04-287-1/+1658
* intel/vec4: Fix constness of vec4_instruction::reads_flag() and ::writes_flag().Francisco Jerez2020-04-281-2/+2
* intel/fs: Replace fs_visitor::bank_conflict_cycles() with stand-alone function.Francisco Jerez2020-04-284-17/+17
* intel/fs: Fix constness of argument of fs_instruction_scheduler::is_compresse...Francisco Jerez2020-04-281-2/+2
* intel/fs: Rename half() helpers to quarter(), allow index up to 3.Francisco Jerez2020-04-284-14/+14
* intel/ir: Add missing initialization of backend_reg::offset during construction.Francisco Jerez2020-04-281-1/+1
* intel/fs/gen12: Fix Render Target Read header setup for new thread payload la...Francisco Jerez2020-04-281-0/+17
* intel/fs/gen12: Work around dual-source blending hangs in combination with SI...Francisco Jerez2020-04-281-2/+3
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-12 14:03:20 +0000