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path: root/src/intel/compiler/brw_eu_defines.h
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* remove final imports.h and imports.c bitsDylan Baker2020-04-211-0/+1
* intel/gen12: Take into account opcode when decoding SWSBCaio Marcelo de Oliveira Filho2020-02-181-2/+5
* intel/fs: Add virtual instruction to load mask of live channels into flag reg...Francisco Jerez2020-02-141-0/+6
* intel/fs: Add SHADER_OPCODE_[IU]SUB_SAT pseudo-opsIan Romanick2020-01-231-0/+6
* intel/fs: Add FS_OPCODE_SCHEDULING_FENCECaio Marcelo de Oliveira Filho2020-01-211-0/+5
* intel/fs: Add DWord scattered read/write opcodesJason Ekstrand2019-11-111-0/+2
* intel/eu/gen12: Add auxiliary type to represent SWSB information during codegen.Francisco Jerez2019-10-111-0/+148
* intel/fs/gen12: Add codegen support for the SYNC instruction.Francisco Jerez2019-10-111-0/+8
* intel/ir/gen12: Add SYNC hardware instruction.Francisco Jerez2019-10-111-0/+1
* intel/eu/gen12: Codegen three-source instruction source and destination regions.Francisco Jerez2019-10-111-0/+1
* intel/ir: Drop hard-coded correspondence between IR and HW opcodes.Francisco Jerez2019-10-111-94/+84
* intel/eu: Rework opcode description tables to allow efficient look-up by eith...Francisco Jerez2019-10-111-1/+3
* i965/fs/generator: add new opcode to set float controls modes in control regi...Samuel Iglesias Gonsálvez2019-09-171-0/+10
* intel/fs: Add support for SLM fence in Gen11Caio Marcelo de Oliveira Filho2019-07-111-0/+11
* intel/compiler: Enable the emission of ROR/ROL instructionsSagar Ghuge2019-07-011-1/+3
* intel/fs: Add an UNDEF instruction to avoid excess live rangesJason Ekstrand2019-06-041-0/+8
* intel/fs: Add support for bindless image load/store/atomicJason Ekstrand2019-04-191-0/+2
* intel/fs: Add support for bindless texture opsJason Ekstrand2019-04-191-0/+5
* anv: Implement VK_KHR_shader_atomic_int64Jason Ekstrand2019-04-191-0/+1
* intel/compiler: Re-prefix non-logical surface opcodes with VEC4Jason Ekstrand2019-02-281-3/+3
* intel/compiler: Drop unused surface opcodesJason Ekstrand2019-02-281-6/+0
* intel/fs: Get rid of the IMAGE_SIZE opcodeJason Ekstrand2019-02-281-1/+0
* intel/fs: Re-order logical surface argumentsJason Ekstrand2019-02-281-2/+2
* intel/fs: Add an enum type for logical sampler inst sourcesJason Ekstrand2019-02-281-0/+15
* intel/fs: Implement nir_intrinsic_global_atomic_*Jason Ekstrand2019-02-011-0/+4
* intel/fs: Implement load/store_global with A64 untyped messagesJason Ekstrand2019-02-011-0/+23
* intel/fs: Use SHADER_OPCODE_SEND for varying UBO pulls on gen7+Jason Ekstrand2019-01-291-1/+0
* intel/fs: Use a logical opcode for IMAGE_SIZEJason Ekstrand2019-01-291-0/+1
* intel/fs: Add a generic SEND opcodeJason Ekstrand2019-01-291-0/+7
* intel/defines: Explicitly cast to uint32_t in SET_FIELD and SET_BITSJason Ekstrand2019-01-291-2/+2
* intel/fs: Remove FS_OPCODE_UNPACK_HALF_2x16_SPLIT opcodes.Francisco Jerez2019-01-091-2/+0
* intel/fs: Support min_lod parameters on texture instructionsJason Ekstrand2018-12-111-0/+2
* intel: Use TXS for image_size when we have a typed surfaceJason Ekstrand2018-08-291-0/+2
* intel/compiler: Implement untyped atomic float min, max, and compare-swap dat...Ian Romanick2018-08-221-1/+11
* intel/ir: Uncomment definition of several unused hardware opcodes.Francisco Jerez2018-07-091-14/+14
* intel/eu: Define SET_BITS helper more easily reusable than SET_FIELD.Francisco Jerez2018-07-091-0/+7
* intel/fs: Get rid of MOV_DISPATCH_TO_FLAGSJason Ekstrand2018-06-281-1/+0
* i965: Add ARB_fragment_shader_interlock support.Plamena Manolova2018-06-011-0/+2
* intel/fs: Replace the CINTERP opcode with a simple MOVFrancisco Jerez2018-05-291-1/+0
* intel/fs: Add support for subgroup quad operationsJason Ekstrand2018-03-071-0/+5
* intel/fs: Add a couple of simple helper opcodesJason Ekstrand2018-03-071-0/+13
* i965/fs: Add support for nir_intrinsic_shuffleJason Ekstrand2018-03-071-0/+9
* i965: Combine {VS,FS}_OPCODE_GET_BUFFER_SIZE opcodes.Kenneth Graunke2017-12-301-3/+2
* i965/fs: Add byte scattered read message and fs supportJose Maria Casanova Crespo2017-12-061-0/+2
* i965/fs: Add byte scattered write message and fs supportJose Maria Casanova Crespo2017-12-061-0/+20
* i965/fs: Add remove_extra_rounding_modes optimizationAlejandro Piñeiro2017-12-061-0/+1
* i965/fs: Define new shader opcode to set rounding modesAlejandro Piñeiro2017-12-061-0/+16
* i965: Add align1 ternary instruction disassembler supportMatt Turner2017-10-201-11/+0
* i965: Add align1 ternary instruction field encodingsMatt Turner2017-10-201-0/+35
* i965: Hide the register type hardware encodingsMatt Turner2017-08-211-31/+0
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