diff options
| author | Caio Marcelo de Oliveira Filho <[email protected]> | 2019-07-10 12:02:23 -0700 |
|---|---|---|
| committer | Caio Marcelo de Oliveira Filho <[email protected]> | 2019-07-11 08:29:32 -0700 |
| commit | b390ff35170fdc2b7f1fb1709a79d81edcd56981 (patch) | |
| tree | 7de3a499d1cab78265da8ff678c2cd3bb486537e /src/intel/compiler/brw_eu_defines.h | |
| parent | 838374b6dd818b6ca09808c4f922d7486ecbd329 (diff) | |
intel/fs: Add support for SLM fence in Gen11
Gen11 SLM is not on L3 anymore, so now the hardware has two separate
fences. Add a way to control which fence types to use.
At this time, we don't have enough information in NIR to control the
visibility of the memory being fenced, so for now be conservative and
assume that fences will need a stall. With more information later
we'll be able to reduce those.
Fixes Vulkan CTS tests in ICL:
dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_nonlocal.workgroup.guard_local.buffer.comp
dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.buffer.guard_nonlocal.workgroup.comp
dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.image.guard_nonlocal.workgroup.comp
dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.workgroup.payload_local.buffer.guard_nonlocal.workgroup.comp
dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.workgroup.payload_local.image.guard_nonlocal.workgroup.comp
The whole set of supported tests in dEQP-VK.memory_model.* group
should be passing in ICL now.
v2: Pass BTI around instead of having an enum. (Jason)
Emit two SHADER_OPCODE_MEMORY_FENCE instead of one that gets
transformed into two. (Jason)
List tests fixed. (Lionel)
v3: For clarity, split the decision of which fences to emit from the
emission code. (Jason)
Reviewed-by: Jason Ekstrand <[email protected]>
Acked-by: Lionel Landwerlin <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_eu_defines.h')
| -rw-r--r-- | src/intel/compiler/brw_eu_defines.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index e8ca7ff8b98..1d4c0b83c87 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -452,6 +452,17 @@ enum opcode { SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL, SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL, + /** + * Memory fence messages. + * + * Source 0: Must be register g0, used as header. + * Source 1: Immediate bool to indicate whether or not we need to stall + * until memory transactions prior to the fence are completed. + * Source 2: Immediate byte indicating which memory to fence. Zero means + * global memory; GEN7_BTI_SLM means SLM (for Gen11+ only). + * + * Vec4 backend only uses Source 0. + */ SHADER_OPCODE_MEMORY_FENCE, SHADER_OPCODE_GEN4_SCRATCH_READ, |