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* freedreno: consolidate GMEM stateRob Clark2020-01-298-19/+24
| | | | | | | | The tile and vsc_pipe arrays are really part of the GMEM configuration. So pull these out of fd_context and into fd_gmem_stateobj. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
* freedreno: extract vsc pipe bo from GMEM stateRob Clark2020-01-297-35/+32
| | | | | | | | | Prep work for reorganizing GMEM state and extracting out of fd_context. The vsc pipe bo was the one thing that doesn't change with GMEM/tile config. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
* iris: Support multiple chained batches.Kenneth Graunke2020-01-292-21/+25
| | | | | | | | | | | There was never much point in artificially limiting chaining to two batches - we can trivially support arbitrary length chains. Currently, we should only ever have 1 or 2, but this may change. Reviewed-by: Tapani Pälli <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3613> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3613>
* iris: Make iris_emit_default_l3_config pull devinfo from the batchKenneth Graunke2020-01-291-5/+4
| | | | | | | No need to pass it, we can just use batch->screen->devinfo. Reviewed-by: Tapani Pälli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3613>
* iris: Drop 'engine' from iris_batch.Kenneth Graunke2020-01-293-13/+2
| | | | | | | | | | | | | | For the moment, everything is I915_EXEC_RENDER, so this isn't necessary. But even should that change, I don't think we want to handle multiple engines in this manner. Nowadays, we have batch->name (IRIS_BATCH_RENDER, IRIS_BATCH_COMPUTE, possibly an IRIS_BATCH_BLIT for blorp batches someday), which describes the functional usage of the batch. We can simply check that and select an engine for that class of work (assuming there ever is more than one). Reviewed-by: Tapani Pälli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3613>
* etnaviv: implement UBOsJonathan Marek2020-01-299-75/+109
| | | | | | | | | | | | | | At the same time, use pre-HALTI2 to use address register for indirect uniform loads, since integers/LOAD instruction isn't always available. Passes all dEQP-GLES3.functional.ubo.* on GC7000L. GC3000 with an extra flush hack passes most of them, but still fails on some of the cases with many loads. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3389> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3389>
* freedreno/a6xx: convert blend state to stateobjRob Clark2020-01-295-53/+54
| | | | | | | | And move to new register builders while we are at it. Signed-off-by: Rob Clark <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3565> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3565>
* freedreno/a6xx: remove special handling based on MRT formatRob Clark2020-01-291-15/+1
| | | | | | | | | Logicop in particular is supposed to work for integer formats.. but maybe this situation doesn't happen in gles. The only thing that isn't required for integer formats is blending. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3565>
* freedreno: use PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLENDRob Clark2020-01-2916-111/+27
| | | | | | | This lets us drop a bunch of special handling for xRGB blend. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3565>
* svga: Avoid discard DMA uploadsThomas Hellstrom2020-01-291-1/+1
| | | | | | | | | | | | Newer versions of the device code will make discard DMA uploads sub-optimal. Disable them for guest-backed aware code, where we previously had them conditionally enabled. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3614>
* compiler: add PERSP to the existing barycentric system valuesSamuel Pitoiset2020-01-294-7/+7
| | | | | | | | We need the LINEAR versions for AMD_shader_explicit_vertex_parameter. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
* iris: Emit CS Stall before Instruction Cache flush for gen12 WAJordan Justen2020-01-281-0/+12
| | | | | | | | | | | Before flushing the instruction cache with a pipe control, we need to use a CS Stall pipe control. Ref: GEN:BUG:1409226450 Rework: Add stall-at-scoreboard (Lionel) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457>
* zink: set compareEnable when setting compareOpErik Faye-Lund2020-01-281-1/+3
| | | | | | | | | | | | | | We need to enable compareEnable for compareOp to be valid, and ANV was recently updated to respect this. So let's update Zink to match. This fixes the shadow-variants of several piglit regressions, like these: spec@arb_shader_texture_lod@execution@tex-miplevel-selection [email protected]@execution@tex-miplevel-selection Fixes: a19cdf989b1 ("anv: only use VkSamplerCreateInfo::compareOp if enabled") Reviewed-by: Eric Engestrom <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3473> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3473>
* iris: Silence warning about AUX_USAGE_MC.Eric Anholt2020-01-281-0/+2
| | | | | | | | It was recently introduced and not added to iris yet it looks like. Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3539>
* radeonsi: Clear uninitialized variableDrew Davenport2020-01-281-1/+1
| | | | | | | | | | | |view| was not initialized leading to flaky test failures in SkQP test unitTest_ES2BlendWithNoTexture. Fixes: 029bfa3d253 "radeonsi: add ability to bind images as image buffers" Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3592> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3592>
* gallium/swr: fix tessellation state save/restoreJan Zielinski2020-01-283-9/+27
| | | | | | | | | | Tessellation state should be saved with TCS/TES state when binding new state and restored if old state is set again. Reviewed-by: Krzysztof Raszkowski <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3596> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3596>
* lima: disable early-z if fragment shader uses discardVasily Khoruzhick2020-01-273-1/+9
| | | | | | | | | | | We have to disable early-z if fragment shader uses discard, otherwise we'll get misrendering. Reported-by: Icenowy Zheng <[email protected]> Reviewed-by: Andreas Baierl <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3570> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3570>
* lima: ppir: always create move and update ld_tex successors for all blocksVasily Khoruzhick2020-01-283-23/+24
| | | | | | | | | | | | Always create a mov for ld_tex since we can't rely on ppir_node_has_single_src_succ() if we have multiple blocks. And since ld_tex successor can be in a different block we have to update their ppir_src as well. Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3564> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3564>
* lima: ppir: don't delete root ld_tex nodes without successors in current blockVasily Khoruzhick2020-01-281-6/+1
| | | | | | | | | | We don't clone ld_tex nodes into each block anymore, so ld_tex may have successors in another block. Fixes: c8554f849e41 ("lima/ppir: don't clone texture loads") Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3564>
* panfrost: Don't copy uniforms when the size is zeroIcecream952020-01-271-1/+1
| | | | | | | | | This fixes a crash when using Gallium HUD with QuakeSpasm when gamma correction shaders (a QuakeSpasm feature, not part of Mesa) are used. Reviewd-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3549> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3549>
* radeonsi: move AMD_DEBUG tests to AMD_TESTPierre-Eric Pelloux-Prayer2020-01-272-11/+23
| | | | | | | | AMD_DEBUG env var is stored in a 64 bits int and has 64 different values. This commit makes some space by moving the test* special values to AMD_TEST. Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3492>
* lima/ppir: fix src read mask swizzlingErico Nunes2020-01-252-11/+13
| | | | | | | | | | | | The src mask can't be calculated from the dest write_mask. Instead, it must be calculated from the swizzled operators of the src. Otherwise, liveness calculation may report incorrect live components for non-ssa registers. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3502> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3502>
* lima/ppir: split ppir_op_undef into undef and dummy againErico Nunes2020-01-253-2/+9
| | | | | | | | | | | | | | | | | | | | | Those were renamed/merged some time ago but it turns out that ppir_op_undef can't be shared. It was being used for undefined ssa operations and for read-before-write operations that may happen to e.g. uninitialized registers (non-ssa) inside a loop. We really don't want to reserve a register for the undef ssa case, but we must reserve and allocate register for the unitialized register case because when it happens inside a loop it may need to hold its value across iterations. This dummy node might be eliminated with a code refactor in ppir in case we are able to emit the write and allocate the ppir_reg before we emit the read. But a major refactor we need this to keep this code to avoid apparent regressions with the new liveness analysis implementation. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3502>
* lima/ppir: fix ssa undef emitErico Nunes2020-01-251-3/+0
| | | | | | | | | | | | The ssa doesn't need to be manually added to block->comp->reg_list. Doing so actually causes other registers to be marked as undef=true later. This patch alone fixes a few deqp tests that have undefs. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3502>
* lima/ppir: handle write to dead registers in ppirErico Nunes2020-01-251-5/+12
| | | | | | | | | | | | | | | | | nir can output writes to dead registers when expanding vec4 operations to non-ssa registers. In that case, some components of the vec4 may be assigned but never read. These are also not currently removed by a nir dead code elimination pass as they are not ssa. In order to prevent regalloc from allocating a live register for this operation, an interference must be assigned to it during liveness analysis. This workaround may be removed in the future if the assignments to dead components can be removed earlier in ppir or nir. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3502>
* radeonsi: fix a regression since the addition of si_shader_llvm_vs.cMarek Olšák2020-01-251-3/+4
| | | | | | | Fixes: cd5b99c541d241d - radeonsi: move VS shader code into si_shader_llvm_vs.c Closes: #2416 Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3561> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3561>
* radeonsi: make screen available to shader part compilationMarek Olšák2020-01-251-0/+4
| | | | | | | to fix a crash in is_multi_part_shader. Fixes: 1a0890dcf30 - radeonsi: change prototypes of si_is_multi_part_shader & si_is_merged_shader Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3561>
* radeonsi: expose shader cache stats to the HUDMarek Olšák2020-01-242-8/+46
| | | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2929> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2929>
* radeonsi: print shader cache stats with AMD_DEBUG=cache_statsMarek Olšák2020-01-244-5/+24
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2929>
* radeonsi: restructure si_shader_cache_load_shaderMarek Olšák2020-01-241-39/+31
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2929>
* radeonsi: use the live shader cacheMarek Olšák2020-01-247-25/+46
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2929>
* panfrost: Fix 32-bit warning for `indices`Alyssa Rosenzweig2020-01-241-1/+1
| | | | | | | | | | | | ../src/gallium/drivers/panfrost/pan_context.c: In function ‘panfrost_draw_vbo’: ../src/gallium/drivers/panfrost/pan_context.c:1551:70: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.indices = (u64) NULL; ^ Signed-off-by: Alyssa Rosenzweig <[email protected]> Reported-by: Icecream95 <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3543> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3543>
* etnaviv: update Android build filesMartin Fuzzey2020-01-241-1/+4
| | | | | | | | | etnaviv no longer builds on Android, fix this. Signed-off-by: Martin Fuzzey <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3447> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3447>
* gallium/swr: implementation of tessellation shaders compilationJan Zielinski2020-01-2416-47/+1885
| | | | | | | | | | | | TCS and TES shaders compilation mechanisms in SWR and state management implementation. Reviewed-by: Krzysztof Raszkowski <[email protected]> Reviewed-by: Bruce Cherniak <[email protected]> Acked-by: Roland Scheidegger <[email protected]> Acked-by: Dave Airlie <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3484> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3484>
* freedreno: Document CP_COND_REG_EXEC moreConnor Abbott2020-01-241-8/+8
| | | | | | | | | The vulkan blob uses the RENDER_MODE mode to condition a blit on the render mode in traces of a dEQP triangle test. Reviewed-by: Rob Clark <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3182> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3182>
* freedreno: Fix OUT_REG() on address regs without a .bo supplied.Eric Anholt2020-01-231-0/+3
| | | | | | | | | Sometimes you want to zero out an address by supplying a NULL BO, but without this we would end up only emitting one dword. Increases size of fd6_gmem.o by .8%, though it's not clear to me why (no obvious terrible codegen happening) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3455>
* lima: use imul for calculations with intrinsic srcVasily Khoruzhick2020-01-231-1/+1
| | | | | | | | | | | It's source is supposed to be int, so we have to use integer multiplication otherwise we'll get undefined result. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3529> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3529>
* pan/decode: Rotate trace filesIcecream952020-01-231-0/+4
| | | | | | Reviewed-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3525> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3525>
* panfrost: Drop mysterious zero=0xFFFF fieldAlyssa Rosenzweig2020-01-231-13/+0
| | | | | | | | | | It doesn't seem to affect any results and it's not at all clear if/why the blob sometimes(?) sets it? So let's clean this up since this solution isn't correct anyway. Signed-off-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3513> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3513>
* radeonsi: separate LLVM compilation from non-LLVM codeMarek Olšák2020-01-231-20/+38
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
* radeonsi: change prototypes of si_is_multi_part_shader & si_is_merged_shaderMarek Olšák2020-01-233-16/+16
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
* radeonsi: make si_compile_shader return boolMarek Olšák2020-01-233-21/+18
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
* radeonsi: make si_compile_llvm return boolMarek Olšák2020-01-234-32/+32
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
* radeonsi: move more LLVM functions into si_shader_llvm.cMarek Olšák2020-01-233-396/+398
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
* radeonsi: fold si_shader_context_set_ir into si_build_main_functionMarek Olšák2020-01-231-29/+16
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
* radeonsi: move si_nir_build_llvm into si_shader_llvm.cMarek Olšák2020-01-232-59/+60
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
* radeonsi: minor cleanup in si_shader_internal.hMarek Olšák2020-01-232-25/+13
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
* radeonsi: move si_shader_llvm_build.c content into si_shader_llvm.cMarek Olšák2020-01-235-183/+153
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
* radeonsi: move VS shader code into si_shader_llvm_vs.cMarek Olšák2020-01-2310-1159/+1188
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
* radeonsi: move non-LLVM code out of si_shader_llvm.cMarek Olšák2020-01-234-37/+31
| | | | | | | There was also some redundant code in si_shader_nir.c Reviewed-by: Timothy Arceri <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-05 14:47:33 +0000