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* iris: Add missing break in switch in modifier_is_supportedJordan Justen2020-07-091-0/+1
| | | | | | | | | | The current fall-through doesn't cause a difference in code flow, but I think we want a break here. Fixes: 2305ab693820 ("iris: Refactor modifier_is_supported for gen12") Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5618>
* iris: fix maybe-uninitialized warning for initial_state variableTimothy Arceri2020-07-081-0/+1
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5766>
* iris: Implement pipe->texture_subdata directlyKenneth Graunke2020-06-261-1/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chris Wilson noted that u_default_texture_subdata's transfer path sometimes results in wasteful double copies. This patch is based on an earlier path he wrote, but updated now that we have staging blits for busy or compressed textures. Consider the case of idle, non-CCS-compressed, tiled images: The transfer-based CPU path has to return a "linear" mapping, so upon map, it mallocs a temporary buffer. u_default_texture_subdata then copies the client memory to this malloc'd buffer, and transfer unmap performs a tiled_memcpy to copy it back into the texture. By writing a direct texture_subdata() implementation, we're able to directly do a tiled_memcpy from the client memory into the destination texture, resulting in only one copy. For linear buffers, there is no advantage to doing things directly, so we simply fall back to u_default_texture_subdata()'s transfer path to avoid replicating those cases. We still may want to use GPU staging buffers for busy destinations (to avoid stalls) or CCS-compressed images (to compress the data), at which point we also fall back to the existing path. We thought to try and use a tiled temporary, but this didn't appear to help. Improves performance in x11perf -shmput500 by 1.96x on my Icelake. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2500 Reviewed-by: Tapani Pälli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3818>
* iris: Honor scanout requirement from DRIDanylo Piliaiev2020-06-251-1/+1
| | | | | | | | | | | | | | | | Translate PIPE_BIND_SCANOUT as ISL_SURF_USAGE_DISPLAY_BIT, instead of PIPE_BIND_DISPLAY_TARGET. PIPE_BIND_DISPLAY_TARGET isn't used for dri images and seem to be set only for fake winsys buffers (which aren't displayed). The trouble is that a fake buffer could be multisampled and we cannot have multisampled surface with display bit. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2313 Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4784>
* iris/bufmgr: Do not use map_gtt or use set/get_tiling on DG1Rafael Antognolli2020-06-221-5/+9
| | | | | | | | | | | | | | | | | | | | | We are starting to see platforms that don't support the get/set tiling uAPI. (For example, DG1.) Additionally on DG1 we shouldn't be using the map_gtt anymore. Let's add some asserts and make sure we don't take those paths accidentally. Rework: * Jordan: Only apply for DG1, not all gen12 * Rafael: Use has_tiling_uapi * Jordan: Copy has_tiling_uapi from devinfo * Jordan: merge in "iris: Rework iris_bo_import_dmabuf() a little." * Jordan: Continue to call get/set_tiling on modifier path Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
* iris: Support I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCSNanley Chery2020-06-191-0/+11
| | | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5420>
* iris: Refactor modifier_is_supported for gen12Nanley Chery2020-06-191-9/+19
| | | | | | | Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5420>
* iris: Handle importing aux-enabled surfaces on TGLNanley Chery2020-06-191-0/+2
| | | | | | | | | | | | Ensure main surfaces are properly 64KB-aligned (as suggested by Jordan) and map the main surface addresses to aux surface addresses on import. v2. Add a Bspec quote. (Sagar) v3. Add a bit more to the Bspec comment. (Ken) Reviewed-by: Jordan Justen <[email protected]> (v2) Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5420>
* iris: Use ISL_AUX_USAGE_GEN12_CCS_E on gen12Nanley Chery2020-06-191-9/+15
| | | | | | | | Makes iris pass a subtest of the fcc-write-after-clear piglit test (fast-clear tracking across layers 1 -> 0 -> 1) on gen12. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5363>
* iris: Don't support sRGB + Y_TILED_CCS on gen9Nanley Chery2020-06-191-4/+2
| | | | | | | | Delete some code that would otherwise need updating for ISL_AUX_USAGE_GEN12_CCS_E. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5363>
* intel: Add ISL_AUX_USAGE_GEN12_CCS_ENanley Chery2020-06-191-0/+2
| | | | | | | | | Add a new aux usage which more accurately describes the behavior of CCS_E on gen12. On this platform, writes using the 3D engine are either compressed or substituted with fast-cleared blocks. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5363>
* iris: Remove the CCS_D fallbackNanley Chery2020-06-191-2/+1
| | | | | | | | | | | | | | | | | | | | | | Remove the CCS_D fallback logic so that iris doesn't attempt to use a non-existent surface state for some renders. Also, add an assertion to catch the issue. The fallback in iris_resource_render_aux_usage can lead to this problem because it doesn't account for the fact that surface states created from resources with the Y_TILED_CCS modifier may only have CCS_E or NONE as aux usages (due to iris_resource_create_with_modifiers). Without this change, the next commit would have triggered the fallback and regressed the following tests on gen9: * dEQP-EGL.functional.wide_color.window_888_colorspace_srgb * dEQP-EGL.functional.wide_color.window_8888_colorspace_srgb * dEQP-EGL.functional.wide_color.pbuffer_888_colorspace_srgb * dEQP-EGL.functional.wide_color.pbuffer_8888_colorspace_srgb Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4972>
* iris: fix export of GEM handlesLionel Landwerlin2020-06-041-6/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We reuse DRM file descriptors internally. Therefore when we export a GEM handle we must do so in the file descriptor used externally. This change also fixes a file descriptor leak of the FD given at screen creation. v2: Don't bother checking fd equals, they're always different Fix dmabuf leak Fix GEM handle leaks by tracking exported handles v3: Check os_same_file_description error (Michel) Don't create multiple exports for a given GEM table v4: Add WARN_ONCE (Ken) Rename external_fd to winsys_fd v5: Remove export lock in favor of bufmgr's Signed-off-by: Lionel Landwerlin <[email protected]> Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2882 Fixes: 7557f1605968 ("iris: share buffer managers accross screens") Tested-by: Eric Engestrom <[email protected]> Tested-by: Tapani Pälli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4861>
* iris: Remove batch argument of iris_resource_prepare_access() and friends.Francisco Jerez2020-06-031-4/+2
| | | | | | | | | | | | The resolves performed by this function are only expected to work from the render batch, so make sure we use it independently of the batch the caller wants to use. This function provides no synchronization guarantees anyway, the caller is expected to insert any cache flushing and synchronization required for the resolved surface to be visible to the target batch. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3875>
* iris: Extend iris_context dirty state flags to 128 bits.Francisco Jerez2020-06-031-3/+4
| | | | | | | | | | | | | We're nearly out of dirty bits, and some patches pending review on GitLab no longer apply due to that. Make room for them by splitting off shader stage-specific bits into a separate stage_dirty mask. An alternative would be to split compute-related bits into a separate mask, but that would prevent the '<< stage' indexing done in various parts of the driver from working. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5279>
* iris: don't assert on unfinished aux import in copy pathsLionel Landwerlin2020-04-301-0/+3
| | | | | | | | | | | | | | | | | After a resource is created the first command using it could be a copy command. In iris_state we finish the import on surface/view creation but we don't do that for copies. v2: Move finish call to gallium entrypoints (Ken) Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2725 Reviewed-by: Tapani Pälli <[email protected]> (v1) Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4657>
* iris: move iris_vtable to iris_screenMike Blumenkrantz2020-04-291-1/+1
| | | | | | | | | instead of inlining this into every context, now a struct is used in the screen struct to reduce memory usage and simplify a couple of the methods Closes: https://gitlab.freedesktop.org/kwg/mesa/-/issues/6 Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4376>
* iris: drop cache coherent cpu mapping for external BOLionel Landwerlin2020-04-151-0/+6
| | | | | | | | | | | | | | | | | | We have to assume any external buffer could be used by the display HW. In the case that buffer is also CPU mapped, we want to assume no cache coherency as it is only available between GT & CPU, not display. Many thanks to Michel Dänzer for the hint! v2: Move cache coherent drop to bufmgr (Chris) v3: Also make BO external if created with PIPE_BIND_SHARED (Eric) Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2552 Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4533>
* iris: make resources take a ref on the screen objectLionel Landwerlin2020-04-111-1/+3
| | | | | | | | | | | | | Because St creates resources from a screen and attach them onto another we need to ensure the resources associated to a screen & bufmgr stay around until we don't need them anymore. Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1373 Reviewed-by: Adam Jackson <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4086>
* iris: properly free resources on BO allocation failureLionel Landwerlin2020-04-111-2/+2
| | | | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Reviewed-by: Adam Jackson <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4086>
* intel/iris: Always initialize CCS to 0Jason Ekstrand2020-03-191-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we were initializing the CCS to 0xFF for MCS+CCS due to a misunderstanding of the following lines in the bspec: The following are the general SW requirements for MCS buffer clear functionality: ... - If Software wants to enable Color Compression without Fast clear, Software needs to initialize MCS with zeros. - Lossless compression and CCS initialized to all F (using HW Fast Clear or SW direct Clear) on the same surface is not supported. The first line does not refer to the CCS as the comment author supposed but refers to the MCS as the comment says. It means that if you want to use MCS compression without a fast-clear, you should initialize the MCS to 0x00. This is because the value 0x00 in the MCS means "all data is in plane 0" which is a perfectly valid non-fast-clear initialization. It's also the value the MCS should be in if you do a RECTLIST slow-clear where the primitive fully covers each pixel such that the same value is written to all samples. The second line in the above quote seems to imply that CCS fast-clear is incompatible with MCS fast-clear. In particular, MCS+CCS fast-clear uses a 0xff value in the MCS (like on Gen7-11) and leaves the CCS in either the compressed or the pass-through state. Therefore, we should initialize the CCS to 0x00 even for MCS+CCS surfaces. Reviewed-by: Sagar Ghuge<[email protected]> Reviewed-by: Nanley Chery <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4074> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4074>
* iris: move existing image format fallback as a helper functionTapani Pälli2020-03-161-0/+26
| | | | | | | | | | | | Patch adds a helper function for determining image format and changes iris_set_shader_images to use it. v2: pass iris_context instead of pipe one, rename function, code cleanup (Nanley) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>
* iris: Use ISL_AUX_USAGE_STC_CCS for stencil CCSJason Ekstrand2020-03-121-3/+11
| | | | | Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
* iris: Use ISL_AUX_USAGE_HIZ_CCS_WT to indicate write-through HiZJason Ekstrand2020-03-121-6/+14
| | | | | | | | | | | | | Previously, we always set the aux_usage to ISL_AUX_USAGE_HIZ_CCS and let ISL choose write-through based on isl_surf_supports_hiz_ccs_wt. This commit makes us choose explicitly at surface creation time whether to use HIZ_CCS or HIZ_CCS_WT based on the same set of conditions. This is more explicit and should be more robust as it lets us choose WT mode in one place rather than trusting isl_surf_supports_hiz_ccs_wt to return the same thing every time. Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
* iris: handle the failure of converting unsupported yuv formats to islJames Xiong2020-02-061-1/+2
| | | | | | Signed-off-by: James Xiong <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3527>
* iris: Silence warning about AUX_USAGE_MC.Eric Anholt2020-01-281-0/+2
| | | | | | | | It was recently introduced and not added to iris yet it looks like. Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3539>
* iris: Avoid replacing backing storage for buffers with no contentsKenneth Graunke2019-12-221-0/+4
| | | | | | We might get asked to pitch the storage on a buffer that already has no meaningful contents. In this case, the existing buffer is as good as a new one.
* iris: Default to X-tiling for scanout buffers without modifiersKenneth Graunke2019-12-111-0/+2
| | | | | | | | | | | | | | | Neither Mutter nor KWin's wayland compositors appear to use modifiers. In the non-modifier case, iris was still trying to use Y-tiling for scan-out surfaces, leading to this error: (gnome-shell:7247): mutter-WARNING **: 09:23:47.787: meta_drm_buffer_gbm_new failed: drmModeAddFB failed: Invalid argument We now fall back to the historical X-tiling for scanout buffers, which ought to work everyone, at lower performance. To regain that, we need to ensure modifiers are actually supported in environments people use. Fixes: fbf31247710 ("iris: Rework tiling/modifiers handling") Reviewed-by: Jason Ekstrand <[email protected]>
* iris: Fix import of multi-planar surfaces with modifiersNanley Chery2019-12-061-1/+5
| | | | | | | | | Multi-planar surfaces are allowed to have modifiers. Don't require DRM_FORMAT_MOD_INVALID in order to create a surface for each plane defined by the format. Fixes: 246eebba4a8 ("iris: Export and import surfaces with modifiers that have aux data") Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Drop 'old_address' parameter from iris_rebind_bufferKenneth Graunke2019-11-251-1/+1
| | | | | | | We can just compare the VERTEX_BUFFER_STATE address field to the current BO's address. When calling rebind, we've already updated the resource to the new buffer, but the state will have the old address.
* util: Move gallium's PIPE_FORMAT utils to /util/format/Eric Anholt2019-11-141-1/+1
| | | | | | | | | | | | | | | To make PIPE_FORMATs usable from non-gallium parts of Mesa, I want to move their helpers out of gallium. Since u_format used util_copy_rect(), I moved that in there, too. I've put it in a separate directory in util/ because it's a big chunk of related code, and it's not clear to me whether we might want it as a separate library from libmesa_util at some point. Closes: #1905 Acked-by: Marek Olšák <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* iris: try to set the specified tiling when importing a dmabufJames Xiong2019-11-041-6/+16
| | | | | | | | | | | | | | | | | | When importing a dmabuf with a specified tiling, the dmabuf user should always try to set the tiling mode because: 1) the exporter can set tiling AFTER exporting/importing. 2) a dmabuf could be exported from a kernel driver other than i915, in this case the dmabuf user and exporter need to set tiling separately. This patch fixes a problem when running vkmark under weston with iris on ICL, it crashed to console with the following assert. i965 doesn't have this problem as it always tries to set the specified tiling mode. weston: ../src/gallium/drivers/iris/iris_resource.c:990: iris_resource_from_handle: Assertion `res->bo->tiling_mode == isl_tiling_to_i915_tiling(res->surf.tiling)' failed. Signed-off-by: James Xiong <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* iris: Align fast clear color state buffer to a page.Rafael Antognolli2019-10-301-0/+5
| | | | | | | | | | | | | | | On gen11 and older, compressed images are tiled and aligned to 4K. On gen12 this 4K alignment restriction was removed. However, only aligning the fast clear color buffer to 64B (a cacheline, as it's on the documentation) is causing some bugs where the fast clear color is not converted during the fast clear operation. Aligning things to 4K seems to fix it. v2: Fix typo case in the comment (Nanley) v3: Rebase and fix conflicts. v4: Fix rebase mistake (Nanley). Reviewed-by: Nanley Chery <[email protected]>
* iris: Allocate main and aux surfaces togetherNanley Chery2019-10-291-34/+21
| | | | | | | | | | | On Gen12, the CCS buffer address doesn't have to be referenced in state packets. In the case of a stencil buffer with CCS, the kernel won't know the location of the CCS unless an extra call is made to pin its address. To avoid this extra call, make the CCS part of the main surface. v2. Update comment above bo_size. (Jordan) Reviewed-by: Jordan Justen <[email protected]>
* iris: Determine aux offsets within configure_auxNanley Chery2019-10-291-10/+9
| | | | | | If a resource has a modifier, the main and aux surfaces will share a BO. Reviewed-by: Jordan Justen <[email protected]>
* iris: Bail resource creation upon aux creation errorNanley Chery2019-10-291-16/+17
| | | | | | | | The functions used during aux buffer configuration and creation only return false for exceptional errors. Don't proceed with surface creation in those cases. Reviewed-by: Jordan Justen <[email protected]>
* iris: Drop iris_resource::aux::extra_aux::boNanley Chery2019-10-291-13/+3
| | | | | | | | The primary and secondary aux buffers are always allocated in the same BO. Suggested-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* iris: Create resource with aux_usage MCS_CCSSagar Ghuge2019-10-281-1/+2
| | | | | Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* iris: Define MCS_CCS state transitions and usagesSagar Ghuge2019-10-281-0/+1
| | | | | | | | v2: 1) Fix assertion check (Nanley Chery) 2) Correct commit subject (Nanley Chery) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* iris: Initialize CCS to fast clear while using with MCSSagar Ghuge2019-10-281-3/+14
| | | | | | | | | | v2: Explain Bsepc quotes properly (Nanley Chery) v3: 1) Fix comment format (Nanley Chery) 2) Fix typo in comment (Nanley Chery) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* iris: Disallow incomplete resource creationNanley Chery2019-10-281-2/+6
| | | | | | | | If a modifier specifies an aux, it must be created. Fixes: 75a3947af46 ("iris/resource: Fall back to no aux if creation fails") Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Don't leak the resource for unsupported modifierNanley Chery2019-10-281-1/+1
| | | | | | | | Make sure the res struct is free'd before returning. Fixes: 2dce0e94a3d ("iris: Initial commit of a new 'iris' driver for Intel Gen8+ GPUs.") Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Enable HIZ_CCS samplingNanley Chery2019-10-281-1/+4
| | | | | Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Enable HIZ_CCS in depth buffer instructionsNanley Chery2019-10-281-2/+6
| | | | | Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Define initial HIZ_CCS state and transitionsNanley Chery2019-10-281-0/+1
| | | | | | | Make it match those of HIZ. Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Create an unusable secondary aux surfaceNanley Chery2019-10-281-6/+39
| | | | | | | | | | | | The HIZ_CCS and MCS_CCS auxiliary surface modes require that drivers store information about two aux buffers. We choose to represent this as HiZ/MCS being the primary aux surface and the CCS as an secondary/extra aux surface. This representation has the effect of placing most of the code that will have to choose between the two aux surfaces around the aux-map entry points. Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Don't guess the aux_usageNanley Chery2019-10-281-96/+72
| | | | | | | | | Instead of guessing an aux_usage, then confirming it if the isl_surf_get_*_surf functions are successful, just call the ISL functions up-front. This will help us to more easily determine if a depth buffer supports HIZ_CCS. Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Support HIZ_CCS in isl_surf_get_ccs_surfNanley Chery2019-10-281-1/+1
| | | | | | | Add an extra aux parameter which will be filled out with CCS if the first two isl_surf parameters fit the requirements for HiZ_CCS. Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Clear ::has_hiz when disabling auxNanley Chery2019-10-281-0/+1
| | | | | Fixes: 2cddc953cd0 ("iris: some initial HiZ bits") Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Allow for non-Y-tiled aux allocationNanley Chery2019-10-281-1/+2
| | | | | | | | The Gen12 CCS is not Y-tiled. Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
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