aboutsummaryrefslogtreecommitdiffstats
path: root/src/gallium/drivers/iris/iris_resource.c
diff options
context:
space:
mode:
authorLionel Landwerlin <[email protected]>2020-04-13 18:14:24 +0300
committerMarge Bot <[email protected]>2020-04-15 09:01:52 +0000
commit8ce46f352e9e2ad103a5058895f3ab4ee164ea33 (patch)
tree869a66e0c8f73ee21615e8cd46acf568a69f177e /src/gallium/drivers/iris/iris_resource.c
parent08a396033be1d7ceddf48da0563a7e4d2cb64429 (diff)
iris: drop cache coherent cpu mapping for external BO
We have to assume any external buffer could be used by the display HW. In the case that buffer is also CPU mapped, we want to assume no cache coherency as it is only available between GT & CPU, not display. Many thanks to Michel Dänzer for the hint! v2: Move cache coherent drop to bufmgr (Chris) v3: Also make BO external if created with PIPE_BIND_SHARED (Eric) Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2552 Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4533>
Diffstat (limited to 'src/gallium/drivers/iris/iris_resource.c')
-rw-r--r--src/gallium/drivers/iris/iris_resource.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c
index 40655bb4032..3476809529d 100644
--- a/src/gallium/drivers/iris/iris_resource.c
+++ b/src/gallium/drivers/iris/iris_resource.c
@@ -801,6 +801,9 @@ iris_resource_create_for_buffer(struct pipe_screen *pscreen,
return NULL;
}
+ if (templ->bind & PIPE_BIND_SHARED)
+ iris_bo_make_external(res->bo);
+
return &res->base;
}
@@ -924,6 +927,9 @@ iris_resource_create_with_modifiers(struct pipe_screen *pscreen,
map_aux_addresses(screen, res);
}
+ if (templ->bind & PIPE_BIND_SHARED)
+ iris_bo_make_external(res->bo);
+
return &res->base;
fail: