aboutsummaryrefslogtreecommitdiffstats
path: root/src/gallium/drivers/freedreno/a5xx
Commit message (Collapse)AuthorAgeFilesLines
* freedreno: small comment re-wordRob Clark2020-07-181-1/+1
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5957>
* freedreno/layout: layout simplifications and pitch from level 0 pitchJonathan Marek2020-07-084-32/+2
| | | | | | | | | | | | This updates a3xx/a4xx/a5xx to fix the fetchsize to "PITCHALIGN" (called "MINLINEOFFSET" by the a3xx docs), and some simplifications to make things more like a6xx. Also similar simplifications for a2xx layout code. The pitch can always be determined using a simple calculation from the base level pitch, so don't pre-calculate a pitch for each mipmap level. Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5796>
* freedreno: add a fd_resource_pitch helperJonathan Marek2020-07-084-20/+15
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5796>
* freedreno/a5xx: set missing bary sysvalsJonathan Marek2020-07-011-10/+25
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5582>
* freedreno/registers: update varying-related registersJonathan Marek2020-07-011-7/+7
| | | | | | | | | | | Note: * a3xx change based on available register documentation * a4xx guesses (RB_RENDER_CONTROL2 bits especially) * a5xx change based on a6xx, these registers seem identical Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5582>
* freedreno/ir3: move finalize_nir to pscreen hookRob Clark2020-06-261-0/+1
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
* freedreno: On a5xx+ INDX_SIZE is MAX_INDICESConnor Abbott2020-06-261-8/+8
| | | | | | | | | This was already done correctly for the indirect variants, and turnip was setting the correct value, but it seems freedreno missed the change in the non-indirect variant. Also, fix a misspelling of "indices" and add a type to INDX_SIZE. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>
* ir3, freedreno: Round up constlen earlierConnor Abbott2020-06-262-2/+4
| | | | | | | Prevents problems when calculating whether we overflow the shared limit. Note that on a6xx, the macros handle the assert for us. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
* freedreno: make foreach_bit() declare it's cursorRob Clark2020-06-251-1/+1
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5634>
* freedreno/a5xx: use point-coord helperRob Clark2020-06-241-33/+25
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
* freedreno/ir3: unify shader create/delete pathsRob Clark2020-06-151-1/+1
| | | | | | | | | In particular, to move the fd_bo create/delete (which is unneeded by turnip) out of the shared ir3 code, it is useful to have a single delete path. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5476>
* freedreno/ir3: split kill from no_earlyzRob Clark2020-06-042-2/+2
| | | | | | | | | Unlike other conditions which prevent early-discard of fragments, kill does not prevent early LRZ test. Split `has_kill` from `no_earlyz` so we can take advantage of this. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5298>
* freedreno: Use explicit *_NONE enum for undefined formatsKristian H. Kristensen2020-05-264-14/+12
| | | | | | | | This adds RB, VFMT and TFMT NONE values for a3xx-a5xx and FMT6_NONE for a6xx. Use those values instead of open coded (enum xxx) ~0 or sometimes even ~0, which triggers out-of-enum range warnings. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5173>
* freedreno/a5xx: Set MIN_LAYERSZ on 3D textures like we do on a6xx.Eric Anholt2020-05-211-0/+2
| | | | | | | | These fields (TILE_ALL and MIN_LAYERSZ) seem to be the same on a5xx as a6xx, having looked at some UBWC vs non-UBWC texturator cases. Setting MIN_LAYERSZ does fix the 3D fail we see in the CTS. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5127>
* freedreno/a5xx: Move resource layout to fdl.Eric Anholt2020-05-211-106/+6
| | | | | | | | | | | I'm working on fixing the 3D layouts in CI so we can stabilize it, but I wanted unit tests using the texturator scripts to make sure I don't break things. This also makes a5xx and a6xx layout easily comparable again. This is a straightforward move of the code with prsc references replaced by arguments in the style of fdl6. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5127>
* freedreno/a5xx: remove unused reference to gmem_alignw in layout codeJonathan Marek2020-05-201-2/+1
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4611>
* freedreno: fix off-by-one in assertions checking for const sizesIlia Mirkin2020-05-171-1/+1
| | | | | | | | | Caused assertions to trip even though everything was fine. The number of constants can be equal to length, so we need less-than-or-equal. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5077>
* freedreno: Drop the "write" arg to emit_const_bo now relocs don't care.Eric Anholt2020-05-121-8/+4
| | | | Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4967>
* freedreno: Replace OUT_RELOCW with OUT_RELOC.Eric Anholt2020-05-129-33/+33
| | | | | | Final cleanup commit now that they're the same. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4967>
* freedreno: Replace OUT_RELOCD with permanently flagging shader BOs for it.Eric Anholt2020-05-121-1/+1
| | | | Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4967>
* freedreno,tu: Don't request fragcoord components not being read.Hyunjun Ko2020-05-082-12/+10
| | | | | | | | | | | | | | | | | v1. Replace the existed bool type with new bitfield and edit register files to take a mask instead of duplicating codes to do masking. v2. Use fragcoord_compmask != 0 instead of fragcoord_compmask > 0 since it represents a bitfield. Tested with dEQP-VK.glsl.builtin_var.simple.fragcoord_xyz/w dEQP-GLES2.functional.shaders.builtin_variable.fragcoord_xyz/w Closes: #2680 Signed-off-by: Hyunjun Ko <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4723>
* freedreno/ir3: inline const emitRob Clark2020-04-303-3/+40
| | | | | | | | | | | | Drop vfunc callbacks for per-gen packet emit, and instead have a header that is #include'd once per gen. We'll end up with multiple copies of some of this, but since we never have multiple gen's of adreno on a single device, only one copy will be paged in (and hopefully in the I-cache for hot-paths) Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>
* gallium: extract out logicop helperRob Clark2020-04-301-17/+1
| | | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4826>
* freedreno: Fix derivatives without texturing on a3xx-a5xx.Eric Anholt2020-04-271-2/+2
| | | | | | The shader variant tells us if we should set the PIXLODENABLE flag. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4685>
* ir3: Skip missing VS outputs in VS out map when linkingConnor Abbott2020-04-251-12/+5
| | | | | | | | | | | | | The hardware is capable of automatically filling in certain values in the VPC without writing them from the last geometry stage, like gl_PointCoord or gl_PrimitiveID when there is no GS. However, we *do* have to enable these outputs (i.e. set the VPC_VAR_DISABLE bit to 0) as VPC_VAR_DISABLE is really about FS inputs rather than VS outputs. To do this, we move the computation of the enable bits to ir3_link_add(), which is also a nice refactor anyway. In addition we detect the PrimID case specifically so that the driver can program the location. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4704>
* freedreno: Make the slice pitch be bytes, not pixels.Eric Anholt2020-04-235-13/+15
| | | | | | | | | | | Back in a2xx, HW pitches were in pixels, so storing that was reasonable. Ever since then, the HW wants pitches in bytes, and we have only one instance of using pitch in pixels in the code (a3xx sysmem path). Flip things around so that only a2xx has to worry about the cpp for looking at pitches. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4558>
* freedreno: Introduce a "cpp_shift" value for cpp divs/muls.Eric Anholt2020-04-231-1/+1
| | | | | | | This only converts part of the driver to use it, leaving the rest to the following commit (which inspired this one). Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4558>
* freedreno: Rename RB_DONE_TSConnor Abbott2020-04-021-2/+2
| | | | | | | This makes the various cache_flush implementations make more sense. Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4065> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4065>
* freedreno: Fix detection of being in a blit for acc queries.Eric Anholt2020-03-301-6/+3
| | | | | | | | | | | | | | | | | The batch might not have stage == FD_STAGE_BLIT set because fd_blitter_pipe_begin was sticking the stage on some random batch (or none at all) rather than the one that would be used in the meta operation. What we actually wanted to be looking at was set_active_query_state(), which is already called by util_blitter and whose state we just needed to track. Fixes piglit occlusion_query_meta_no_fragments. I haven't changed query_hw.c's stage handling to clean the rest up because I don't have a db410c/db820c at home to iterate over the piglit tests. Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4356> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4356>
* freedreno: Count blits in GL_TIME_ELAPSED and perf counter queries.Eric Anholt2020-03-301-2/+2
| | | | | | Fixes 0 gpu time reported for glBlitFramebuffer in apitrace replay --pgpu. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4356>
* freedreno/a5xx: Fix min-vs-mag filtering decisions on non-mipmap tex.Eric Anholt2020-03-171-1/+10
| | | | | | | | | This a port of 3338d6e5f8b5 ("freedreno/a3xx: Mostly fix min-vs-mag filtering decisions on non-mipmap tex.") Reviewed-by: Kristian H. Kristensen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4177> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4177>
* freedreno: name sysmem color/depth flush eventsJonathan Marek2020-02-141-1/+1
| | | | | | | Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3814>
* freedreno: Move the layout debug under FD_MESA_DEBUG=layout.Eric Anholt2020-02-041-9/+0
| | | | | | | I keep wanting to turn this on while debugging layout stuff, and I suspect krh and robclark could use it too. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3059>
* gallium: Add and use a helper for packing uc from a color_union.Eric Anholt2020-02-041-7/+1
| | | | | | | | The same pattern kept coming up, and we don't need to hit util_format_write_4* to do it when we have util_format_pack_rgba(). Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2744>
* freedreno: remove flush-queueRob Clark2020-01-291-1/+1
| | | | | | Signed-off-by: Rob Clark <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
* freedreno: get GMEM state from batchRob Clark2020-01-291-13/+10
| | | | | | | Prep work to reduce churn in next patch. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
* freedreno/a5xx: constify gmem stateRob Clark2020-01-291-10/+10
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
* freedreno: constify fd_vsc_pipeRob Clark2020-01-291-2/+2
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
* freedreno: constify fd_tileRob Clark2020-01-291-4/+4
| | | | | | | | | In a following patch, when we cache the gmem state, we will want to treat the gmem state as immuatable. So start converting things to const to make this more clear.. fd_tile is a good place to start. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
* freedreno: consolidate GMEM stateRob Clark2020-01-291-2/+3
| | | | | | | | The tile and vsc_pipe arrays are really part of the GMEM configuration. So pull these out of fd_context and into fd_gmem_stateobj. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
* freedreno: extract vsc pipe bo from GMEM stateRob Clark2020-01-291-7/+6
| | | | | | | | | Prep work for reorganizing GMEM state and extracting out of fd_context. The vsc pipe bo was the one thing that doesn't change with GMEM/tile config. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
* freedreno: use PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLENDRob Clark2020-01-293-22/+5
| | | | | | | This lets us drop a bunch of special handling for xRGB blend. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3565>
* compiler: add PERSP to the existing barycentric system valuesSamuel Pitoiset2020-01-291-1/+1
| | | | | | | | We need the LINEAR versions for AMD_shader_explicit_vertex_parameter. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
* freedreno: Stop scattered remapping of SSBOs/images to IBOs.Eric Anholt2020-01-212-6/+3
| | | | | | | | | | | | | | | | | | | | | | | Just make it be all SSBOs then all storage images. The remapping table was there to make it so that the big gap present from gallium's atomic lowering would get cleaned up, but that's no longer case. The table has made it very hard to support Vulkan storage images, so it's time for it to go. This does mean that an SSBO/IBO that is only loaded (or size-queried) will now occupy a slot in the table where it wouldn't before. This seems like a minor cost compared to being able to drop this much logic. With the remapping table gone, SSBO array handling for turnip just falls out. Fixes many array cases of dEQP-VK.binding_model.shader_access.primary_cmd_buf.storage_buffer.* Reviewed-by: Rob Clark <[email protected]> Reviewed-by: Jonathan Marek <[email protected]> (turnip) Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3240> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3240>
* freedreno/a5xx+a6xx: split LRZ layout to per-genRob Clark2019-12-101-0/+31
| | | | | | Seems to be a bit different for a6xx, so let's split this out. Signed-off-by: Rob Clark <[email protected]>
* freedreno: reorder format checkFritz Koenig2019-12-061-2/+2
| | | | | | | | | | | | | | With the addition of the planar formats helper, the planar formats no longer have a valid block.bits field. Calling util_format_get_blocksize therefore asserts. Reorder the check to see if the format is supported before doing the query to get the blocksize. Fixes: 20f132e5eff2d ("gallium/util: add planar format layouts and helpers") Signed-off-by: Fritz Koenig <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno: switch to layout helperRob Clark2019-11-266-39/+39
| | | | | | | | | | | | The slices table and most of the other layout fields in the freedreno_resource moves into fdl_layout. v2: Changes by anholt to not have duplicate fields, which was introducing a surprising behavior change in resource layout (using the level_linear helper before the setup of the shadowed fields) Reviewed-by: Eric Anholt <[email protected]> Acked-by: Rob Clark <[email protected]>
* freedreno: Convert the slice struct to the new resource header.Eric Anholt2019-11-265-9/+9
| | | | | | | | This gets the worst of the sed required for shared resource layout out of the way. The texture layout comment is dropped now that we're referencing the shared header, which has a more complete description. Acked-by: Rob Clark <[email protected]>
* freedreno: Introduce a fd_resource_tile_mode() helper.Eric Anholt2019-11-263-10/+5
| | | | | | | | Multiple places were doing the same thing to get the tile mode of a level, so refactor it out. This will make the shared resource helper transition cleaner. Acked-by: Rob Clark <[email protected]>
* freedreno: use rsc->slice accessor everywhereRob Clark2019-11-263-7/+10
| | | | | | | This will make it easier to extract the slice table out into a layout helper. Acked-by: Rob Clark <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-02 02:55:11 +0000