diff options
| author | Connor Abbott <[email protected]> | 2020-04-22 17:54:41 +0200 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-04-25 01:06:21 +0000 |
| commit | 1f9839907a8eee15f634ff95577fbe498f1b70c2 (patch) | |
| tree | 60333ae38634083ecdbc1e6367a4315d1eb7173a /src/gallium/drivers/freedreno/a5xx | |
| parent | cc530858c1e6adb761fca163f49432fbc71348b9 (diff) | |
ir3: Skip missing VS outputs in VS out map when linking
The hardware is capable of automatically filling in certain values in
the VPC without writing them from the last geometry stage, like
gl_PointCoord or gl_PrimitiveID when there is no GS. However, we *do*
have to enable these outputs (i.e. set the VPC_VAR_DISABLE bit to 0) as
VPC_VAR_DISABLE is really about FS inputs rather than VS outputs. To do
this, we move the computation of the enable bits to ir3_link_add(),
which is also a nice refactor anyway. In addition we detect the PrimID
case specifically so that the driver can program the location.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4704>
Diffstat (limited to 'src/gallium/drivers/freedreno/a5xx')
| -rw-r--r-- | src/gallium/drivers/freedreno/a5xx/fd5_program.c | 17 |
1 files changed, 5 insertions, 12 deletions
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_program.c b/src/gallium/drivers/freedreno/a5xx/fd5_program.c index b427f989470..a2fe505b4dd 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_program.c +++ b/src/gallium/drivers/freedreno/a5xx/fd5_program.c @@ -410,24 +410,17 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring, COND(s[VS].v->num_samp > 0, A5XX_SP_VS_CTRL_REG0_PIXLODENABLE)); struct ir3_shader_linkage l = {0}; - ir3_link_shaders(&l, s[VS].v, s[FS].v); + ir3_link_shaders(&l, s[VS].v, s[FS].v, true); if ((s[VS].v->shader->stream_output.num_outputs > 0) && !emit->binning_pass) link_stream_out(&l, s[VS].v); - BITSET_DECLARE(varbs, 128) = {0}; - uint32_t *varmask = (uint32_t *)varbs; - - for (i = 0; i < l.cnt; i++) - for (j = 0; j < util_last_bit(l.var[i].compmask); j++) - BITSET_SET(varbs, l.var[i].loc + j); - OUT_PKT4(ring, REG_A5XX_VPC_VAR_DISABLE(0), 4); - OUT_RING(ring, ~varmask[0]); /* VPC_VAR[0].DISABLE */ - OUT_RING(ring, ~varmask[1]); /* VPC_VAR[1].DISABLE */ - OUT_RING(ring, ~varmask[2]); /* VPC_VAR[2].DISABLE */ - OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */ + OUT_RING(ring, ~l.varmask[0]); /* VPC_VAR[0].DISABLE */ + OUT_RING(ring, ~l.varmask[1]); /* VPC_VAR[1].DISABLE */ + OUT_RING(ring, ~l.varmask[2]); /* VPC_VAR[2].DISABLE */ + OUT_RING(ring, ~l.varmask[3]); /* VPC_VAR[3].DISABLE */ /* a5xx appends pos/psize to end of the linkage map: */ if (pos_regid != regid(63,0)) |