diff options
| author | Hyunjun Ko <[email protected]> | 2020-05-07 06:06:59 +0000 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-05-08 17:45:03 +0000 |
| commit | 094c7646a3ae4980f76605a922572fe2ed78f6f1 (patch) | |
| tree | 5a33b702839a74969ce74456055fb4b18d03ed91 /src/gallium/drivers/freedreno/a5xx | |
| parent | ab5590e92bc36e2b785a088751c433d31989d778 (diff) | |
freedreno,tu: Don't request fragcoord components not being read.
v1. Replace the existed bool type with new bitfield and edit register
files to take a mask instead of duplicating codes to do masking.
v2. Use fragcoord_compmask != 0 instead of fragcoord_compmask > 0 since
it represents a bitfield.
Tested with
dEQP-VK.glsl.builtin_var.simple.fragcoord_xyz/w
dEQP-GLES2.functional.shaders.builtin_variable.fragcoord_xyz/w
Closes: #2680
Signed-off-by: Hyunjun Ko <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4723>
Diffstat (limited to 'src/gallium/drivers/freedreno/a5xx')
| -rw-r--r-- | src/gallium/drivers/freedreno/a5xx/fd5_emit.c | 6 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/a5xx/fd5_program.c | 16 |
2 files changed, 10 insertions, 12 deletions
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c index 140c7c5f510..1f23d8ae225 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c +++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c @@ -613,11 +613,13 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring, OUT_PKT4(ring, REG_A5XX_RB_DEPTH_PLANE_CNTL, 1); OUT_RING(ring, COND(fragz, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) | - COND(fragz && fp->frag_coord, A5XX_RB_DEPTH_PLANE_CNTL_UNK1)); + COND(fragz && fp->fragcoord_compmask != 0, + A5XX_RB_DEPTH_PLANE_CNTL_UNK1)); OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL, 1); OUT_RING(ring, COND(fragz, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) | - COND(fragz && fp->frag_coord, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1)); + COND(fragz && fp->fragcoord_compmask != 0, + A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1)); } /* NOTE: scissor enabled bit is part of rasterizer state: */ diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_program.c b/src/gallium/drivers/freedreno/a5xx/fd5_program.c index 72f9f99335f..21d94dc72e2 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_program.c +++ b/src/gallium/drivers/freedreno/a5xx/fd5_program.c @@ -487,7 +487,7 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring, OUT_PKT4(ring, REG_A5XX_VPC_CNTL_0, 1); OUT_RING(ring, A5XX_VPC_CNTL_0_STRIDE_IN_VPC(l.max_loc) | COND(s[FS].v->total_in > 0, A5XX_VPC_CNTL_0_VARYING) | - COND(s[FS].v->frag_coord, A5XX_VPC_CNTL_0_VARYING) | + COND(s[FS].v->fragcoord_compmask != 0, A5XX_VPC_CNTL_0_VARYING) | 0x10000); // XXX fd5_context(ctx)->max_loc = l.max_loc; @@ -518,7 +518,7 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring, OUT_PKT4(ring, REG_A5XX_SP_FS_CTRL_REG0, 1); OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_SP_FS_CTRL_REG0_VARYING) | - COND(s[FS].v->frag_coord, A5XX_SP_FS_CTRL_REG0_VARYING) | + COND(s[FS].v->fragcoord_compmask != 0, A5XX_SP_FS_CTRL_REG0_VARYING) | 0x40006 | /* XXX set pretty much everywhere */ A5XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) | A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) | @@ -537,19 +537,15 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring, OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1); OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_GRAS_CNTL_VARYING) | - COND(s[FS].v->frag_coord, A5XX_GRAS_CNTL_XCOORD | - A5XX_GRAS_CNTL_YCOORD | - A5XX_GRAS_CNTL_ZCOORD | - A5XX_GRAS_CNTL_WCOORD | + COND(s[FS].v->fragcoord_compmask != 0, + A5XX_GRAS_CNTL_COORD_MASK(s[FS].v->fragcoord_compmask) | A5XX_GRAS_CNTL_UNK3) | COND(s[FS].v->frag_face, A5XX_GRAS_CNTL_UNK3)); OUT_PKT4(ring, REG_A5XX_RB_RENDER_CONTROL0, 2); OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_RB_RENDER_CONTROL0_VARYING) | - COND(s[FS].v->frag_coord, A5XX_RB_RENDER_CONTROL0_XCOORD | - A5XX_RB_RENDER_CONTROL0_YCOORD | - A5XX_RB_RENDER_CONTROL0_ZCOORD | - A5XX_RB_RENDER_CONTROL0_WCOORD | + COND(s[FS].v->fragcoord_compmask != 0, + A5XX_RB_RENDER_CONTROL0_COORD_MASK(s[FS].v->fragcoord_compmask) | A5XX_RB_RENDER_CONTROL0_UNK3) | COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL0_UNK3)); OUT_RING(ring, |