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* mesa: allow MAX_DUAL_SOURCE_DRAW_BUFFERS to be available to ESRyan Houdek2015-11-191-1/+3
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: enable usage of blend_func_extended blend factors in GLES2Ryan Houdek2015-11-191-3/+3
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* glapi: add EXT_blend_func_extended XML definitionsRyan Houdek2015-11-191-0/+8
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: Don't expose GL_EXT_shader_integer_mix in GLES 1.xIan Romanick2015-11-181-1/+1
| | | | | | | | | There are no shaders, so it doesn't even make sense to expose the extension. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Cc: Nanley Chery <[email protected]>
* i965: Allow indirect GS input indexing in the scalar backend.Kenneth Graunke2015-11-184-46/+107
| | | | | | | | | | | | | | | | | | This allows arbitrary non-constant indices on GS input arrays, both for the vertex index, and any array offsets beyond that. All indirects are handled via the pull model. We could potentially handle indirect addressing of pushed data as well, but it would add additional code complexity, and we usually have to pull inputs anyway due to the sheer volume of input data. Plus, marking pushed inputs as live due to indirect addressing could exacerbate register pressure problems pretty badly. We'd need to be careful. v2: Use updated MOV_INDIRECT opcode. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Abdiel Janulgue <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/nir: Add hooks for testing nir_shader_cloneJason Ekstrand2015-11-181-9/+26
| | | | | | | | | | This commit adds code for testing nir_shader_clone by running it after each and every optimization pass and throwing away the old shader. Testing nir_shader_clone is hidden behind a new INTEL_CLONE_NIR environment variable. Reviewed-by: Rob Clark <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/nir: Validate that NIR passes call nir_metadata_preserve().Kenneth Graunke2015-11-181-3/+7
| | | | | | | | | | | | | | | | | | | | | Failing to call nir_metadata_preserve() can have nasty consequences: some pass breaks dominance information, but leaves it marked as valid, causing some subsequent pass to go haywire and probably crash. This pass adds a simple validation mechanism to ensure passes handle this properly. We add a new bogus metadata flag that isn't used for anything in particular, set it before each pass, and ensure it *isn't* still set after the pass. nir_metadata_preserve will reset the flag, so correct passes will work, and bad passes will assert fail. (I would have made these functions static inline, but nir.h is included in C++, so we can't bit-or enums without lots of casting...) Thanks to Dylan Baker for the idea. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/nir: Add OPT() and OPT_V() macros for invoking NIR passes.Kenneth Graunke2015-11-181-72/+59
| | | | | | | | | | | | | | | | | OPT() is the normal macro for passes that return booleans, while OPT_V() is a variant that works for passes that don't properly report progress. (Such passes should be fixed to return a boolean, eventually.) These macros take care of calling nir_validate_shader() and setting progress appropriately. In the future, it would be easy to add shader dumping similar to INTEL_DEBUG=optimizer by extending the macro. v2 (Jason Ekstrand): - Fix an unused variable warning Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Add enums for 3DSTATE_TE field values.Kenneth Graunke2015-11-181-0/+28
| | | | | | | | | | | | | 3DSTATE_TE has partitioning, output topology, and domain fields, each of which has several enumerated values. We'll also need to switch on the domain, so enums (rather than #defines) seem like a natural fit. I chose to put these in brw_compiler.h because they'll be stored in struct brw_tes_prog_data, which will live there. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* meta/generate_mipmap: Don't leak the framebuffer objectIan Romanick2015-11-181-0/+5
| | | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Cc: "10.6 11.0" <[email protected]>
* i965: Prevent fast clears for MSRTs on SKLNeil Roberts2015-11-181-0/+7
| | | | | | | | | | | | | | | | | | | | | | | There are currently a bunch of formats that behave strangely when sampling the cleared color from the MCS buffer on SKL. They seem to mostly be formats that don't have an alpha component, although it's not all of them, and we haven't yet found anything in the specs which would explain this. For now to be on the safe side this patch just prevents fast clears for MSRTs on SKL altogether so that when fast clears are eventually enabled it will only be for single-sampled surfaces. The assumption is that clears are probably more likely to be used in single-sampled applications anyway so we can at least get them working and we can enable MSRTs later once we understand the problem better. This patch should have no functional effect other than perhaps receiving fewer perf_debug messages on SKL+. v2: Improve the commit message to avoid saying the patch disables fast clears because it will be merged before fast clears are enabled for any surfaces so it doesn't actually disable anything. Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Fix PIPE_CONTOL typo.Kenneth Graunke2015-11-171-1/+1
| | | | PIPE_CONTOL!!!
* i965: Add assertion for src_stencil payload sizeBen Widawsky2015-11-171-0/+6
| | | | | | | | | | This helps address a coverity warning and prevents future questions about this code. Reported-by: Coverity (via Ilia) Cc: Ilia Mirkin <[email protected]> Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Implement ARB_pipeline_statistics_query tessellation counters.Kenneth Graunke2015-11-171-8/+8
| | | | | | | | | | We basically just need to uncomment Ben's code. v2: Fix obvious bugs caught by Ben. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Add INTEL_DEBUG=shader_time support for tessellation shaders.Kenneth Graunke2015-11-172-0/+14
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* i965: Add INTEL_DEBUG=tcs,tes and hs,ds flags for tessellation shaders.Kenneth Graunke2015-11-172-2/+8
| | | | | | | | | | | | | Even though both tessellation shader stages must be used together, I still think it makes sense to add separate debug flags for each stage. It makes it possible to read the TCS/HS, rule out problems, then read the TES/DS separately, without sifting through as much printed text. I decided to add both the GL names (tcs/tes) and hardware names (hs/ds) so they can be used interchangeably. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* i965: Add more MAX_*_URB_ENTRY_SIZE_BYTES #defines.Kenneth Graunke2015-11-171-0/+6
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Abdiel Janulgue <[email protected]>
* i965: Add missing stdio.h include to brw_compiler.h.Kenneth Graunke2015-11-171-0/+1
| | | | | | | | | | | | This is needed for the FILE * type in brw_print_vue_map(). Apparently, all files that include brw_compiler.h already pick this up via some include chain, so this isn't actually a build fix. However, I have patches which introduce new consumers of brw_compiler.h that fail to build because of the missing #include. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Return the correct value type from brw_compile_gs()Eduardo Lima Mitev2015-11-171-1/+1
| | | | | | | | | | | | | | | brw_compile_gs() should return a pointer to unsigned, but it is returning the bool 'false' at some point, hence annoying us with a compiler warning: In function 'const unsigned int* brw::brw_compile_gs(const brw_compiler*, void*, void*, const brw_gs_prog_key*, brw_gs_prog_data*, const nir_shader*, gl_shader_program*, int, unsigned int*, char**)': brw_vec4_gs_visitor.cpp:776:14: warning: converting 'false' to pointer type 'const unsigned int*' [-Wconversion-null] return false; ^ Reviewed-by: Jordan Justen <[email protected]>
* mesa: do runtime validation of precision varyings only on ESTapani Pälli2015-11-171-3/+13
| | | | | | | | | Precision qualifier should be ignored on desktop OpenGL. v2: include spec quote (Samuel) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Set MaxCombinedUniformBlocks properly.Kenneth Graunke2015-11-161-0/+1
| | | | | | | | | | Up until now, we've been letting core Mesa initialize it to 36 for us (which is presumably BRW_MAX_UBO (12) * (VS+GS+FS stages -> 3)). With compute and tessellation, we need to increase this. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Clean up context constant initialization code.Kenneth Graunke2015-11-161-80/+54
| | | | | | | | | | | | | | | | | | | | | | | | This was getting pretty out of hand, and with compute partially in place and tessellation on the way, it was only going to get worse. This patch makes a "stage exists?" predicate and a "number of stages" count and uses them to clean up a lot of calculations. We can just loop over shader stages and set things for the ones that exist. For combined counts, we can just multiply by the number of stages. It also tries to organize a little bit. We should probably use _mesa_has_geometry_shaders/tessellation/compute here, but we can't because ctx->Version isn't initialized yet. Perhaps that could be fixed in the future. No change in "glxinfo -l" on Broadwell. v2: Drop stray compute shader hunk. Mark stage_exists as const. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Convert scalar_* flags to a scalar_stage array.Kenneth Graunke2015-11-1610-39/+27
| | | | | | | | | I was going to add scalar_tcs and scalar_tes flags, and then thought better of it and decided to convert this to an array. Simpler. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* r200: fix bgrx8/xrgb8 blitsRoland Scheidegger2015-11-171-0/+4
| | | | | | | | | | | | | | | | | Since 779cabfc7d022de8b7b9bc7fdac0caffa8646c51 the same txformat table entries are used for "normal" texturing as well as for blits. However, I forgot to put in an entry for the bgrx8 (le) and xrgb8 (be) formats - the normal texturing path can't hit them because the radeon tex format chooser will never chose them, but we get that format from the dri buffers (at least I assume we got it from there). This is untested but essentially addressing the same bug as for radeon. (I don't think that the second entry per le/be table is actually necessary, but shouldn't hurt...) Tested-by: Ian Romanick <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: "11.0" <[email protected]>
* radeon: fix bgrx8/xrgb8 blitsRoland Scheidegger2015-11-171-0/+2
| | | | | | | | | | | | | | | | Since d21320f6258b2e1780a15c1ca718963d8a15ca18 the same txformat table entries are used for "normal" texturing as well as for blits. However, I forgot to put in an entry for the bgrx8 (le) and xrgb8 (be) formats - the normal texturing path can't hit them because the radeon tex format chooser will never chose them, but we get that format from the dri buffers (at least I assume we got it from there). This caused lots of piglit regressions (and probably lots of trouble outside piglit too). This fixes bug https://bugs.freedesktop.org/show_bug.cgi?id=92900. Tested-by: Ian Romanick <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: "11.0" <[email protected]>
* meta/generate_mipmap: Only modify the draw framebuffer binding in ↵Ian Romanick2015-11-161-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | fallback_required Previously GL_FRAMEBUFFER was used. However, if GL_EXT_framebuffer_blit is supported (note: it is supported by every Mesa driver), this is *sometimes* an alias for GL_DRAW_FRAMEBUFFER (getters) and *sometimes* an alias for *both* GL_DRAW_FRAMEBUFFER and GL_READ_FRAMEBUFFER (setters). As a result, the code saved one binding but modified both. If the bindings were different, the GL_READ_FRAMEBUFFER would be incorrect on exit. Fixes the piglit fbo-generatemipmap-versus-READ_FRAMEBUFFER test. Ideally this function would use DSA functions and not modify the binding at all. However, that would be a much more intrusive change because _mesa_meta_bind_fbo_image would also need to be modified. _mesa_meta_bind_fbo_image has a lot of callers. Much of this code is about to get a major rework due to bug #92363, so I don't think it matters too much. In fact, I discovered this bug while working on the other bug. Le bon temps! Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Cc: "10.6 11.0" <[email protected]>
* i965: Introduce a MOV_INDIRECT opcode.Kenneth Graunke2015-11-146-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The geometry and tessellation control shader stages both read from multiple URB entries (one per vertex). The thread payload contains several URB handles which reference these separate memory segments. In GLSL, these inputs are represented as per-vertex arrays; the outermost array index selects which vertex's inputs to read. This array index does not necessarily need to be constant. To handle that, we need to use indirect addressing on GRFs to select which of the thread payload registers has the appropriate URB handle. (This is before we can even think about applying the pull model!) This patch introduces a new opcode which performs a MOV from a source using VxH indirect addressing (which allows each of the 8 SIMD channels to select distinct data.) Based on a patch by Jason Ekstrand. v2: Rename from INDIRECT_THREAD_PAYLOAD_MOV to MOV_INDIRECT; make it a bit more generic. Use regs_read() instead of hacking up the register allocator. (Suggested by Jason Ekstrand.) v3: Fix regs_read() to be more accurate for small unaligned regions. Also rebase on Matt's work. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> [v3] Reviewed-by: Abdiel Janulgue <[email protected]> [v1]
* i965: Add a SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT opcode.Kenneth Graunke2015-11-134-5/+10
| | | | | | | | | | | We need to use per-slot offsets when there's non-uniform indexing, as each SIMD channel could have a different index. We want to use them for any non-constant index (even if uniform), as it lives in the message header instead of the descriptor, allowing us to set offsets in GRFs rather than immediates. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Abdiel Janulgue <[email protected]>
* i965: Print input/output VUE maps on INTEL_DEBUG=vs, gs.Kenneth Graunke2015-11-134-1/+40
| | | | | | | | | | | | I've been carrying around a patch to do this for the last few months, and it's been exceedingly useful for debugging GS and tessellation problems. I've caught lots of bugs by inspecting the interface expectations of two adjacent stages. It's not that much spam, so I figure we may as well just print it. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Matt Turner <[email protected]>
* i965: Make convert_attr_sources_to_hw_regs handle stride == 0.Kenneth Graunke2015-11-131-1/+2
| | | | | | | | | | | | This makes expressions like component(fs_reg(ATTR, n), 7) get a proper <0,1,0> region instead of the invalid <0,8,0>. Nobody uses this today, but I plan to. v2: Rebase on Matt's changes; simplify. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> [v1]
* i965: Silence unused parameter warnings in get_buffer_rectIan Romanick2015-11-131-4/+3
| | | | | | | | | | | | | brw_meta_fast_clear.c: In function 'get_buffer_rect': brw_meta_fast_clear.c:318:37: warning: unused parameter 'brw' [-Wunused-parameter] get_buffer_rect(struct brw_context *brw, struct gl_framebuffer *fb, ^ brw_meta_fast_clear.c:319:44: warning: unused parameter 'irb' [-Wunused-parameter] struct intel_renderbuffer *irb, struct rect *rect) ^ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* meta/generate_mipmap: Don't leak the sampler objectIan Romanick2015-11-131-0/+2
| | | | | | Signed-off-by: Ian Romanick <[email protected]> Cc: "10.6 11.0" <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Remove unneeded #includes.Matt Turner2015-11-131-4/+0
| | | | | Some of these are no longer needed since all the backends switched to NIR.
* i965: Silence warning.Matt Turner2015-11-131-2/+2
| | | | | | | | | | | | | | intel_asm_annotation.c: In function ‘annotation_insert_error’: intel_asm_annotation.c:214:18: warning: ‘ann’ may be used uninitialized in this function [-Wmaybe-uninitialized] ann->error = ralloc_strdup(annotation->mem_ctx, error); ^ I initially tried changing the type of ann_count to unsigned (is currently int), since that in addition to the check that it's non-zero at the beginning of the function seems sufficient to prove that it must be greater than zero. Unfortunately that wasn't sufficient.
* i965: Don't write beyond allocated memory.Juha-Pekka Heikkila2015-11-131-1/+1
| | | | | | Reviewed-by: Eduardo Lima Mitev <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Juha-Pekka Heikkila <[email protected]>
* i965: Use BRW_MRF_COMPR4 macro in more places.Matt Turner2015-11-134-6/+6
| | | | | Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Combine register file field.Matt Turner2015-11-137-34/+27
| | | | | | | | The first four values (2-bits) are hardware values, and VGRF, ATTR, and UNIFORM remain values used in the IR. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Replace HW_REG with ARF/FIXED_GRF.Matt Turner2015-11-1313-211/+157
| | | | | | | | | | | | | | | | HW_REGs are (were!) kind of awful. If the file was HW_REG, you had to look at different fields for type, abs, negate, writemask, swizzle, and a second file. They also caused annoying problems like immediate sources being considered scheduling barriers (commit 6148e94e2) and other such nonsense. Instead use ARF/FIXED_GRF/MRF for fixed registers in those files. After a sufficient amount of time has passed since "GRF" was used, we can rename FIXED_GRF -> GRF, but doing so now would make rebasing awful. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Set stride correctly for immediates in fs_reg(brw_reg).Matt Turner2015-11-131-0/+6
| | | | | | | | | | | | | | | | | | The fs_reg() constructors for immediates set stride to 0, except for vector-immediates, which set stride to 1. This patch makes the fs_reg constructor that takes a brw_reg do likewise, so that stride is set correctly for cases such as fs_reg(brw_imm_v(...)). The generator asserts that this is true (and presumably it's useful in some optimization passes?) and the VF fs_reg constructors did this (by virtue of the fact that it doesn't override what init() does). In the next commit, calling this constructor with brw_imm_* will generate an IMM file register rather than a HW_REG, making this change necessary to avoid breakage with existing uses of brw_imm_v(). Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Handle type-V immediates in brw_reg_from_fs_reg().Matt Turner2015-11-131-0/+3
| | | | | | | | | We use brw_imm_v() to produce type-V immediates, which generates a brw_reg with fs_reg's .file set to HW_REG. The next commit will rid us of HW_REGs, so we need to handle BRW_REGISTER_TYPE_V in the IMM case. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Rename GRF to VGRF.Matt Turner2015-11-1330-194/+194
| | | | | | | | | | The 2-bit hardware register file field is ARF, GRF, MRF, IMM. Rename GRF to VGRF (virtual GRF) so that we can reuse the GRF name to mean an assigned general purpose register. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move BAD_FILE from the beginning of enum register_file.Matt Turner2015-11-131-1/+1
| | | | | | | | | I'm going to begin using brw_reg's file field in backend_reg and its derivatives, and in order to keep the hardware value for ARF as 0, we have to do something different. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Initialize registers.Matt Turner2015-11-133-2/+18
| | | | | | | | | | | | The test (file == BAD_FILE) works on registers for which the constructor has not run because BAD_FILE is zero. The next commit will move BAD_FILE in the enum so that it's no longer zero. In the case of this->outputs, the constructor was being run implicitly, and we were unnecessarily memsetting is to zero. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use brw_reg's nr field to store register number.Matt Turner2015-11-1325-290/+276
| | | | | | | | | | | | In addition to combining another field, we get replace silliness like "reg.reg" with something that actually makes sense, "reg.nr"; and no one will ever wonder again why dst.reg isn't a dst_reg. Moving the now 16-bit nr field to a 16-bit boundary decreases code size by about 3k. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Unwrap some lines.Matt Turner2015-11-134-12/+4
| | | | | Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Remove swizzle/writemask fields from src/dst_reg.Matt Turner2015-11-132-8/+1
| | | | | | | | Also allows us to handle HW_REGs in the swizzle() and writemask() functions. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove fixed_hw_reg field from backend_reg.Matt Turner2015-11-1311-162/+139
| | | | | | | | Since backend_reg now inherits brw_reg, we can use it in place of the fixed_hw_reg field. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use immediate storage in inherited brw_reg.Matt Turner2015-11-1310-95/+96
| | | | | Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add and use enum brw_reg_file.Matt Turner2015-11-134-19/+23
| | | | | Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Reorganize brw_reg fields.Matt Turner2015-11-131-8/+8
| | | | | | | | | Put fields that are meaningless with an immediate in the same storage with the immediate. This leaves fields type, file, nr, subnr in the first dword where there's now extra room for expansion. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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