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* r300: shut up valgrindMaciej Cencora2009-03-072-2/+2
* i965: check if we run out of GRF/temp registersBrian Paul2009-03-061-1/+25
* i965: bump up BRW_EU_MAX_INSNBrian Paul2009-03-061-1/+1
* i965: commentsBrian Paul2009-03-061-0/+2
* i965: comments and minor clean-upsBrian Paul2009-03-061-3/+43
* i965: avoid unnecessary calls to brw_wm_is_glsl()Brian Paul2009-03-064-2/+12
* r300: fix depth write regression (found by Nicolai Haehnle)Maciej Cencora2009-03-061-3/+10
* r300: enable EXT_fog_coord extensionMaciej Cencora2009-03-062-161/+20
* r300: route fog coord and W pos correctlyMaciej Cencora2009-03-062-42/+106
* r300: rewrite and hopefully simplify RS setupMaciej Cencora2009-03-063-213/+225
* r300: add few macros for RS setupMaciej Cencora2009-03-061-0/+6
* r300: silence valgrindMaciej Cencora2009-03-061-1/+1
* r300: Print reg address when debugging is enabledMaciej Cencora2009-03-061-4/+14
* r300: don't crash on sw tcl hw if point size vertex attrib is sentMaciej Cencora2009-03-061-2/+2
* intel: Fix bpp setting of blits to 8bpp targets.Eric Anholt2009-03-051-0/+2
* i965: fix 3DPRIMITIVE batch decode of the vertex count field.Eric Anholt2009-03-051-1/+1
* i965: Stop dumping programs after the first all-zeroes entry.Eric Anholt2009-03-051-0/+8
* intel: Add always_flush_batch driconf option for making small batchbuffers.Eric Anholt2009-03-056-1/+25
* intel: Add always_flush_cache driconf option for debugging cache flush failure.Eric Anholt2009-03-057-2/+42
* i965: Add a note about why the _NEW_STENCIL is required in draw_buffers.Eric Anholt2009-03-051-0/+5
* intel: Remove a gratuitous MI_FLUSH after clearing with a blit.Eric Anholt2009-03-051-1/+0
* i965: Remove dead flushing code.Eric Anholt2009-03-054-23/+0
* i965: comments and formatting fixesBrian Paul2009-03-051-4/+14
* i965: fix emit_math1() function used for scalar instructionsBrian Paul2009-03-051-9/+32
* i965: fix screen depth test in intel_validate_framebuffer)_Brian Paul2009-03-051-1/+2
* i965: init dest reg CondMask = COND_TR (the proper default)Brian Paul2009-03-051-2/+2
* i965: add software fallback for conformant 3D textures and GL_CLAMPRobert Ellison2009-03-044-10/+40
* mesa: call _mesa_get_cpu_string() to get CPU info for GL_RENDERER stringBrian Paul2009-03-041-66/+8
* mesa: use Stencil._Enabled field instead of Stencil.EnabledBrian Paul2009-03-0216-19/+19
* mesa: remove unused AUX buffersBrian Paul2009-03-021-4/+1
* mesa: rename, reorder FRAG_RESULT_x tokensBrian Paul2009-02-288-15/+15
* intel: remove some unneeded buffer unmap callsBrian Paul2009-02-271-14/+2
* i915: Add support for a new G33-like chipset.Shaohua Li2009-02-272-2/+13
* i965: texture fixes: bordered textures, fallback renderingRobert Ellison2009-02-271-3/+31
* intel: no-op the intel_finish_render_texture() functionBrian Paul2009-02-261-13/+10
* intel: check texture formats in intel_validate_framebuffer()Brian Paul2009-02-261-0/+29
* intel: updated comment, some debug code (disabled)Brian Paul2009-02-261-3/+12
* i965: rename draw_regions -> color_regionsroot2009-02-264-20/+20
* i965: add missing init for region->widthBrian Paul2009-02-261-1/+2
* mesa: replace old prog_instruction::Sampler field with Aux fieldBrian Paul2009-02-263-10/+9
* i965: whitespace/indentation fixesBrian Paul2009-02-261-28/+24
* intel: Revert disable of accelerated Bitmap, which slipped in with spans stuff.Eric Anholt2009-02-261-2/+2
* i965: fix for RHW workaroundXiang, Haihao2009-02-262-43/+99
* intel: Disable creating DRI2 FBconfigs with depth size != color size.Eric Anholt2009-02-261-1/+22
* intel: Add span code for z24 without stencil.Eric Anholt2009-02-261-2/+22
* intel: make template wrappers for the spans templates.Eric Anholt2009-02-254-189/+165
* intel: Fix up x8r8g8b8 renderbuffer format so that alpha=1 spans code happens.Eric Anholt2009-02-252-1/+17
* i965: Rename CMD_CONST_BUFFER_STATE to the CS_URB_STATE used in the docs.Eric Anholt2009-02-256-13/+14
* R300: Add support for RS600 chipsAlex Deucher2009-02-252-2/+12
* i965: fix line stipple fallback for GL_LINE_STRIP primitivesRobert Ellison2009-02-231-1/+1
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