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* mesa: Rename 4 color component unsigned byte MESA_FORMATsMark Mueller2014-01-2710-34/+34
| | | | | | | | | | | | | Change all 4 color component unsigned byte formats to meet spec for P Type formats: s/MESA_FORMAT_RGBA8888\b/MESA_FORMAT_A8B8G8R8_UNORM/g s/MESA_FORMAT_RGBA8888_REV\b/MESA_FORMAT_R8G8B8A8_UNORM/g s/MESA_FORMAT_ARGB8888\b/MESA_FORMAT_B8G8R8A8_UNORM/g s/MESA_FORMAT_ARGB8888_REV\b/MESA_FORMAT_A8R8G8B8_UNORM/g s/MESA_FORMAT_RGBX8888\b/MESA_FORMAT_X8B8G8R8_UNORM/g s/MESA_FORMAT_RGBX8888_REV\b/MESA_FORMAT_R8G8B8X8_UNORM/g s/MESA_FORMAT_XRGB8888\b/MESA_FORMAT_B8G8R8X8_UNORM/g s/MESA_FORMAT_XRGB8888_REV\b/MESA_FORMAT_X8R8G8B8_UNORM/g
* mesa: change gl_format to mesa_formatMark Mueller2014-01-2717-58/+58
| | | | s/\bgl_format\b/mesa_format/g. Use better name for Mesa Formats enum
* mesa: GL_EXT_framebuffer_blit is not optionalIan Romanick2014-01-271-1/+0
| | | | | | | | | Every driver supports it. All current and future Gallium drivers always support it, and all existing classic drivers support it. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Don't store qpitch / 4 as mt->qpitch for compressed surfaces.Kenneth Graunke2014-01-252-5/+8
| | | | | | | | | | | | | | | | | | | | Broadwell requires software to specify QPitch in a bunch of packets, so we decided to store it in the miptree. However, when I did that refactoring, I missed a subtlety: the hardware expects QPitch to be "in units of rows in the uncompressed surface". This is the value we originally compute. However, for compressed surfaces, we then divided it by 4 (the block height), to obtain the physical layout. This is no longer the QPitch Broadwell expects. So, store the original undivided value in mt->qpitch, but continue to use the divided value in brw_miptree_layout_texture_array(). For non-Broadwell platforms, this should have no impact at all. Helps fix Piglit's "getteximage-targets S3TC CUBE" test on Broadwell. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7: Use to the correct program when uploading transform feedback state.Paul Berry2014-01-232-10/+6
| | | | | | | | | | | | Transform feedback may come from either the geometry shader or the vertex shader, so we can't use ctx->Shader.CurrentProgram[MESA_SHADER_VERTEX] to find the current post-link transform feedback information. Fortunately we can use ctx->TransformFeedback.CurrentObject->shader_program. Cc: 10.0 <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove *_generator::shader field; use prog field instead.Paul Berry2014-01-237-18/+8
| | | | | | | | | | | | | | | The "shader" field in fs_generator, vec4_generator, and gen8_generator was only used for one purpose; to figure out if we were compiling an assembly program or a GLSL shader (shader is NULL for assembly programs). And it wasn't being used properly: in vec4 shaders we were always initializing it based on prog->_LinkedShaders[MESA_SHADER_FRAGMENT], regardless of whether we were compiling a geometry shader or a vertex shader. This patch simplifies things by using the "prog" field instead; this is also NULL for assembly programs. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: switch eu-emitter to use FS IR and fs_generatorTopi Pohjolainen2014-01-233-120/+84
| | | | | | | | | | | | | | | | | | No regressions on IVB (piglit quick + unit tests). v2 (Paul): - no need to patch the unit tests anymore. Original logic was altered and unit tests updated to match the fs-generator - lrp emission moves from the blorp compiler core into the emitter here (previously there was a separate refactoring patch which is not really needed anymore as the lrp logic got refactored when the original lrp logic got fixed). - pass 'BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX' to the generator in fs_inst::target instead of hardcoding it Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: add support for BRW_OPCODE_AVG in fs_generatorTopi Pohjolainen2014-01-231-0/+3
| | | | | | | Needed for compiling blorp blit programs. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: introduce blorp specific rt-write for fs_generatorTopi Pohjolainen2014-01-234-0/+23
| | | | | | | | | | | | | | | | | The compiler for blorp programs likes to emit instructions for the message construction itself meaning that the generator needs to skip any such when blorp programs are translated for the hw. In addition, the binding table control is special for blorp programs and the generator does not need to update the binding tables associated with the compiler bookkeeping (this in fact gets thrown away as the blorp compiler sets the program data in its own way). v2 (Paul): do not hardcode the binding table index but use fs_inst::target instead. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: allow unit tests to dump the final patched assemblyTopi Pohjolainen2014-01-232-8/+10
| | | | | | | | | | | | | | Unit tests comparing generated blorp programs to known good need to have the dump in designated file instead of in default standard output. The comparison also expects the jump counters of if-else-instructions to be correctly set and hence the dump needs to be taken _after_ 'patch_IF_ELSE()' is run (the default dump of the fs_generator does this before). v2 (Paul): dropped the redundant 'dump_enabled' argument Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap brw_IF/ELSE/ENDIF() into eu-emitterTopi Pohjolainen2014-01-232-9/+23
| | | | | | | v2 (Paul): renamed emit_if() to emit_cmp_if() Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap RNDD (/brw_RNDD(&func, /emit_rndd(/)Topi Pohjolainen2014-01-232-2/+8
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap FRC (/brw_FRC(&func, /emit_frc(/)Topi Pohjolainen2014-01-232-4/+10
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap MUL (/brw_MUL(&func, /emit_mul(/)Topi Pohjolainen2014-01-232-9/+16
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap OR (/brw_OR(&func, /emit_or(/)Topi Pohjolainen2014-01-232-24/+31
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap SHL (/brw_SHL(&func, /emit_shl(/)Topi Pohjolainen2014-01-232-12/+19
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap SHR (/brw_SHR(&func, /emit_shr(/)Topi Pohjolainen2014-01-232-12/+19
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap ADD (/brw_ADD(&func, /emit_add(/)Topi Pohjolainen2014-01-232-18/+32
| | | | | | | | In addition, the special case requiring explicit execution size control is wrapped manually. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap AND (/brw_AND(&func, /emit_and(/)Topi Pohjolainen2014-01-232-39/+46
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap MOV (/brw_MOV(&func, /emit_mov(/)Topi Pohjolainen2014-01-232-35/+45
| | | | | | | | In addition, the two special cases requiring explicit execution size control are wrapped manually. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap emission of if-equal-assignmentTopi Pohjolainen2014-01-232-24/+12
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap emission of conditional assignmentTopi Pohjolainen2014-01-232-15/+15
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: move emission of sample combining into eu-emitterTopi Pohjolainen2014-01-233-9/+24
| | | | | | | | | v2 (Paul): pass the combining opcode as an argument to emit_combine(). This keeps manual_blend_average() selfcontained documentation wise. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: move emission of rt-write into eu-emitterTopi Pohjolainen2014-01-233-10/+28
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: move emission of texture lookup into eu-emitterTopi Pohjolainen2014-01-233-22/+60
| | | | | | | | | | | Resolving of the hardware message type is moved into the emitter also in preparation for switching to use fs_generator. The generator wants to translate the high level op-code into the message type and hence the emitter needs to know the original op-code. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: introduce non-compressed equivalent of tex_cmsTopi Pohjolainen2014-01-234-0/+13
| | | | | | | v2: introduces 'SHADER_OPCODE_TXF_UMS' also for gen8 Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: rename tex_ms to tex_cmsTopi Pohjolainen2014-01-2310-17/+17
| | | | | | | | | | Prepares for the introduction of non-compressed multi-sampled lookup used in the blorp programs. v2: now also taking into account gen8 Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: move emission of pixel kill into eu-emitterTopi Pohjolainen2014-01-233-25/+38
| | | | | | | | | The combination of four separate comparison operations and and the masked "and" require special treatment when moving to FS LIR. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: introduce separate eu-emitter for blit compilerTopi Pohjolainen2014-01-234-38/+113
| | | | | | | | | | | | Prepares for presenting blorp blit programs using FS IR that allows EU-assembly generation using i965 glsl-compiler backend (fs_generator). v2: rebased on top of endif-jump counter fix (moving the added brw_set_uip_jip() into the emitter) Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Support 32 texture image units on Haswell+.Kenneth Graunke2014-01-222-4/+7
| | | | | | | | | | | | | | | | | | | | The Intel closed source OpenGL driver recently began supporting 32 texture image units on Haswell. This makes the open source driver support 32 as well. Earlier generations don't have the message header field required to support more than 16 sampler states, so we continue to advertise 16 there. On Haswell, this causes us to advertise: - GL_MAX_TEXTURE_IMAGE_UNITS = 32 - GL_MAX_VERTEX_TEXTURE_IMAGE_UNITS = 32 - GL_MAX_COMBINED_TEXTURE_IMAGE_UNITS = 96 instead of the old values of 16, 16, and 48. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Switch from BRW_MAX_TEX_UNIT to the actual limit.Kenneth Graunke2014-01-221-1/+2
| | | | | | | | | | BRW_MAX_TEX_UNIT is about to grow, but only Gen7+ will be able to support the new larger value. On older platforms, we don't want to allocate the extra space - it would just be a waste. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/vec4: Support arbitrarily large sampler state indices on Haswell+.Kenneth Graunke2014-01-222-3/+26
| | | | | | | | | | Like the scalar backend, we add an offset to the "Sampler State Pointer" field to select a group of 16 samplers, then use the "Sampler Index" field to select within that group. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/vec4: Refactor sampler message setup.Kenneth Graunke2014-01-221-17/+22
| | | | | | | | | | The next patch adds an additional case where the message header is necessary. So we want to do the g0 copy if inst->header_present is set, rather than inst->texture_offset. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/vec4: Don't set header_present if texel offsets are all 0.Kenneth Graunke2014-01-221-9/+8
| | | | | | | | | | | | | | In theory, a shader might use textureOffset() but set all the texel offsets to zero. In that case, we don't actually need to set up the message header - zero is the implicit default. By moving the texture_offset setup before the header_present setup, we can easily only set header_present when there are non-zero texel offset values. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Support arbitrarily large sampler state indices on Haswell+.Kenneth Graunke2014-01-222-2/+22
| | | | | | | | | | | | | | | | | The message descriptor's "Sampler Index" field is only 4 bits (on all generations of hardware), so it can only represent indices 0 through 15. Haswell introduced a new field in the message header - "Sampler State Pointer". Normally, this is copied straight from g0, but we can also add a byte offset (as long as it's a multiple of 32). This patch uses a "Sampler State Pointer" offset to select a group of 16 sampler states, and then uses the "Sampler Index" field to select the state within that group. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Plumb sampler index into emit_texture_gen7.Kenneth Graunke2014-01-223-4/+4
| | | | | | | | We'll need this in the next patch. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Refactor sampler message header to duplicate less code.Kenneth Graunke2014-01-221-25/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, the code to copy g0 to the message header existed in two places - one for the texture offset case, and one for any other case. By treating texture_offset as a special case of header_present, we can remove this duplication and shorten the code. Future patches which add new header fields also won't have to add additional duplication. This also clarifies a confusing construct. The old code contained: } else if (inst->header_present) { if (brw->gen >= 7) { ...explicit copy from g0 to the message header... } else { /* Set up an implied move from g0 to the MRF. */ } } This looks like it might set up an implied move on Sandybridge, which doesn't support those. However, Sandybridge only uses a message header for texture offsets, so it would never hit this code path. The new code avoids this implicit knowledge by only setting up an implied move on Gen4-5. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Use get_element_ud to shorten texture header access.Kenneth Graunke2014-01-221-2/+1
| | | | | | | | This is shorter, easier to read, and further from the 80 column limit. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* intel: Fix initial MakeCurrent for single-buffer drawablesKristian Høgsberg2014-01-221-6/+4
| | | | | | | | | | | | | | | Commit 05da4a7a5e7d5bd988cb31f94ed8e1f053d9ee39 attempts to eliminate the call to intel_update_renderbuffer() in the case where we already have a drawbuffer for the drawable. Unfortunately this only checks the back left renderbuffer, which breaks in case of single buffer drawables. This means that the initial viewport will not be set in that case. Instead, we now check whether the initial viewport has not been set, in which case we call out to intel_update_renderbuffer(). https://bugs.freedesktop.org/show_bug.cgi?id=73862 Signed-off-by: Kristian Høgsberg <[email protected]>
* i965/blorp: use BRW_COMPRESSION_2NDHALF for second half LPRTopi Pohjolainen2014-01-222-28/+42
| | | | | | | | | No known bugs fixed but this is now in line with fs-generator. No regresssions on IVB. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: patch jump counters also for endifTopi Pohjolainen2014-01-222-3/+5
| | | | | | | | | | | | | | | | | No known bugs fixed but this is now in line with fs-generator. No regresssions on IVB. Eric further explained that: "The endif jump, since it's forward, is just an optimization to have set right -- otherwise, the GPU will just step forward instruction by instruction until it hits something else that updates the per-channel PC." Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix comments to refer to the new ctx->Shader.CurrentProgram array.Paul Berry2014-01-213-6/+6
| | | | | Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Fold long lines introduced by the previous patch.Paul Berry2014-01-214-8/+14
| | | | | Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Replace ctx->Shader.Current{Vertex,Fragment,Geometry}Program with an ↵Paul Berry2014-01-2113-19/+19
| | | | | | | | | | | | | | | | | | | | | array. These are replaced with ctx->Shader.CurrentProgram[MESA_SHADER_{VERTEX,FRAGMENT,GEOMETRY}]. In patches to follow, this will allow us to replace a lot of ad-hoc logic with a variable index into the array. With the exception of the changes to mtypes.h, this patch was generated entirely by the command: find src -type f '(' -iname '*.c' -o -iname '*.cpp' ')' \ -print0 | xargs -0 sed -i \ -e 's/\.CurrentVertexProgram/.CurrentProgram[MESA_SHADER_VERTEX]/g' \ -e 's/\.CurrentGeometryProgram/.CurrentProgram[MESA_SHADER_GEOMETRY]/g' \ -e 's/\.CurrentFragmentProgram/.CurrentProgram[MESA_SHADER_FRAGMENT]/g' Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Replace _mesa_program_index_to_target with _mesa_shader_stage_to_program.Paul Berry2014-01-211-1/+1
| | | | | | | | | | | | | | | | In my recent zeal to refactor Mesa's handling of the gl_shader_stage enum, I accidentally wound up with two functions that do the same thing: _mesa_program_index_to_target(), and _mesa_shader_stage_to_program(). This patch keeps _mesa_shader_stage_to_program(), since its name is more consistent with other related functions. However, it changes the signature so that it accepts an unsigned integer instead of a gl_shader_stage--this avoids awkward casts when the function is called from C++ code. Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965: Ignore 'centroid' interpolation qualifier in case of persample shadingAnuj Phogat2014-01-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch handles the use of 'centroid' qualifier with 'in' variables in a fragment shader when persample shading is enabled. Per sample shading for the whole fragment shader can be enabled by: glEnable(GL_SAMPLE_SHADING) or using {gl_SamplePosition, gl_SampleID} builtin variables in fragment shader. Explaining it below in more detail. /* Enable sample shading using OpenGL API */ glEnable(GL_SAMPLE_SHADING); glMinSampleShading(1.0); Example fragment shader: in vec4 a; centroid in vec4 b; main() { ... } Variable 'a' will be interpolated at sample location. But, what interpolation should we use for variable 'b' ? ARB_sample_shading recommends interpolation at sample position for all the variables. GLSL 400 (and earlier) spec says that: "When an interpolation qualifier is used, it overrides settings established through the OpenGL API." But, this text got deleted in later versions of GLSL. NVIDIA's and AMD's proprietary linux drivers (at OpenGL 4.3) interpolates at sample position. This convinces me to use the similar approach on intel hardware. Cc: [email protected] Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Use sample barycentric coordinates with per sample shadingAnuj Phogat2014-01-214-6/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current implementation of arb_sample_shading doesn't set 'Barycentric Interpolation Mode' correctly. We use pixel barycentric coordinates for per sample shading. Instead we should select perspective sample or non-perspective sample barycentric coordinates. It also enables using sample barycentric coordinates in case of a fragment shader variable declared with 'sample' qualifier. e.g. sample in vec4 pos; A piglit test to verify the implementation has been posted on piglit mailing list for review. V2: Do not interpolate all the 'in' variables at sample position if fragment shader uses 'sample' qualifier with one of them. For example we have a fragment shader: #version 330 #extension ARB_gpu_shader5: require sample in vec4 a; in vec4 b; main() { ... } Only 'a' should be sampled at sample location, not 'b'. Cc: [email protected] Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Add an option to ignore sample qualifierAnuj Phogat2014-01-213-4/+4
| | | | | | | | | | This will be useful in my next patch which depends on a functionality of _mesa_get_min_invocations_per_fragment() to ignore the sample qualifier (prog->IsSample) based on a flag passed to it. Cc: [email protected] Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Optimize LRP with x == y into a MOV.Matt Turner2014-01-211-0/+10
| | | | | | | | | total instructions in shared programs: 1487331 -> 1485988 (-0.09%) instructions in affected programs: 45638 -> 44295 (-2.94%) GAINED: 7 LOST: 0 Reviewed-by: Jordan Justen <[email protected]>
* i965: Enable AOS optimizations for the geometry shader.Matt Turner2014-01-211-0/+1
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
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