mesa: change gl_format to mesa_format

s/\bgl_format\b/mesa_format/g. Use better name for Mesa Formats enum

17 files changed, 58 insertions, 58 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 0939a317867..e7f6328d431 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -115,7 +115,7 @@ brw_blorp_surface_info::set(struct brw_context *brw,
       this->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM;
       break;
    default: {
-      gl_format linear_format = _mesa_get_srgb_format_linear(mt->format);
+      mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
       if (is_render_target) {
          assert(brw->format_supported_as_render_target[linear_format]);
          this->brw_surfaceformat = brw->render_target_format[linear_format];
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index c4d1108bcdf..00f37b37469 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -197,10 +197,10 @@ do_blorp_blit(struct brw_context *brw, GLbitfield buffer_bit,
 }
 
 static bool
-color_formats_match(gl_format src_format, gl_format dst_format)
+color_formats_match(mesa_format src_format, mesa_format dst_format)
 {
-   gl_format linear_src_format = _mesa_get_srgb_format_linear(src_format);
-   gl_format linear_dst_format = _mesa_get_srgb_format_linear(dst_format);
+   mesa_format linear_src_format = _mesa_get_srgb_format_linear(src_format);
+   mesa_format linear_dst_format = _mesa_get_srgb_format_linear(dst_format);
 
    /* Normally, we require the formats to be equal.  However, we also support
     * blitting from ARGB to XRGB (discarding alpha), and from XRGB to ARGB
@@ -222,8 +222,8 @@ formats_match(GLbitfield buffer_bit, struct intel_renderbuffer *src_irb,
     * example MESA_FORMAT_X8_Z24 and MESA_FORMAT_S8_Z24), and we can blit
     * between those formats.
     */
-   gl_format src_format = find_miptree(buffer_bit, src_irb)->format;
-   gl_format dst_format = find_miptree(buffer_bit, dst_irb)->format;
+   mesa_format src_format = find_miptree(buffer_bit, src_irb)->format;
+   mesa_format dst_format = find_miptree(buffer_bit, dst_irb)->format;
 
    return color_formats_match(src_format, dst_format);
 }
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index c55108a69fd..94672e00e35 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -147,7 +147,7 @@ brw_blorp_const_color_program::~brw_blorp_const_color_program()
  */
 static bool
 is_color_fast_clear_compatible(struct brw_context *brw,
-                               gl_format format,
+                               mesa_format format,
                                const union gl_color_union *color)
 {
    if (_mesa_is_format_integer_color(format))
@@ -193,7 +193,7 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct brw_context *brw,
    dst.set(brw, irb->mt, irb->mt_level, layer, true);
 
    /* Override the surface format according to the context's sRGB rules. */
-   gl_format format = _mesa_get_render_format(ctx, irb->mt->format);
+   mesa_format format = _mesa_get_render_format(ctx, irb->mt->format);
    dst.brw_surfaceformat = brw->render_target_format[format];
 
    x0 = fb->_Xmin;
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 42d40e67cfb..8d098e6c3b7 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1644,7 +1644,7 @@ void brw_upload_abo_surfaces(struct brw_context *brw,
                              struct brw_stage_prog_data *prog_data);
 
 /* brw_surface_formats.c */
-bool brw_is_hiz_depth_format(struct brw_context *ctx, gl_format format);
+bool brw_is_hiz_depth_format(struct brw_context *ctx, mesa_format format);
 bool brw_render_target_supported(struct brw_context *brw,
                                  struct gl_renderbuffer *rb);
 
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 56754b2f76c..77b8aa63007 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -188,12 +188,12 @@ void gen4_init_vtable_surface_functions(struct brw_context *brw);
 uint32_t brw_get_surface_tiling_bits(uint32_t tiling);
 uint32_t brw_get_surface_num_multisamples(unsigned num_samples);
 
-uint32_t brw_format_for_mesa_format(gl_format mesa_format);
+uint32_t brw_format_for_mesa_format(mesa_format mesa_format);
 
 GLuint translate_tex_target(GLenum target);
 
 GLuint translate_tex_format(struct brw_context *brw,
-                            gl_format mesa_format,
+                            mesa_format mesa_format,
 			    GLenum srgb_decode);
 
 int brw_get_texture_swizzle(const struct gl_context *ctx,
diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c
index 9b75c2b8abb..ebbd335c536 100644
--- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
+++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
@@ -310,7 +310,7 @@ const struct surface_format_info surface_formats[] = {
 #undef Y
 
 uint32_t
-brw_format_for_mesa_format(gl_format mesa_format)
+brw_format_for_mesa_format(mesa_format mesa_format)
 {
    /* This table is ordered according to the enum ordering in formats.h.  We do
     * expect that enum to be extended without our explicit initialization
@@ -530,7 +530,7 @@ brw_init_surface_formats(struct brw_context *brw)
 {
    struct gl_context *ctx = &brw->ctx;
    int gen;
-   gl_format format;
+   mesa_format format;
 
    memset(&ctx->TextureFormatSupported, 0, sizeof(ctx->TextureFormatSupported));
 
@@ -654,7 +654,7 @@ bool
 brw_render_target_supported(struct brw_context *brw,
 			    struct gl_renderbuffer *rb)
 {
-   gl_format format = rb->Format;
+   mesa_format format = rb->Format;
 
    /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
     * we would consider them renderable even though we don't have surface
@@ -685,7 +685,7 @@ brw_render_target_supported(struct brw_context *brw,
 
 GLuint
 translate_tex_format(struct brw_context *brw,
-                     gl_format mesa_format,
+                     mesa_format mesa_format,
 		     GLenum srgb_decode)
 {
    struct gl_context *ctx = &brw->ctx;
@@ -732,7 +732,7 @@ translate_tex_format(struct brw_context *brw,
 
 /** Can HiZ be enabled on a depthbuffer of the given format? */
 bool
-brw_is_hiz_depth_format(struct brw_context *brw, gl_format format)
+brw_is_hiz_depth_format(struct brw_context *brw, mesa_format format)
 {
    if (!brw->has_hiz)
       return false;
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index f5ea13437ae..a7e4ddd3a28 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -40,7 +40,7 @@
 
 static unsigned int
 intel_horizontal_texture_alignment_unit(struct brw_context *brw,
-                                       gl_format format)
+                                       mesa_format format)
 {
    /**
     * From the "Alignment Unit Size" section of various specs, namely:
@@ -86,7 +86,7 @@ intel_horizontal_texture_alignment_unit(struct brw_context *brw,
 
 static unsigned int
 intel_vertical_texture_alignment_unit(struct brw_context *brw,
-                                      gl_format format, bool multisampled)
+                                      mesa_format format, bool multisampled)
 {
    /**
     * From the "Alignment Unit Size" section of various specs, namely:
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index c7386103c7b..dd96c9bfd3c 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -237,7 +237,7 @@ brw_update_buffer_texture_surface(struct gl_context *ctx,
       intel_buffer_object(tObj->BufferObject);
    uint32_t size = tObj->BufferSize;
    drm_intel_bo *bo = NULL;
-   gl_format format = tObj->_BufferObjectFormat;
+   mesa_format format = tObj->_BufferObjectFormat;
    uint32_t brw_format = brw_format_for_mesa_format(format);
    int texel_size = _mesa_get_format_bytes(format);
 
@@ -596,7 +596,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
    uint32_t tile_x, tile_y;
    uint32_t format = 0;
    /* _NEW_BUFFERS */
-   gl_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
+   mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
    uint32_t surf_index =
       brw->wm.prog_data->binding_table.render_target_start + unit;
 
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index ff10ec84d56..12d0fa9de58 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -444,7 +444,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
    struct intel_region *region = irb->mt->region;
    uint32_t format;
    /* _NEW_BUFFERS */
-   gl_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
+   mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
    uint32_t surftype;
    bool is_array = false;
    int depth = MAX2(rb->Depth, 1);
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index 4d2218a9ce3..82720d174dd 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -162,8 +162,8 @@ intel_miptree_blit(struct brw_context *brw,
     * consistent with what we want in the callers (glCopyTexSubImage(),
     * glBlitFramebuffer(), texture validation, etc.).
     */
-   gl_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
-   gl_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
+   mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
+   mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
 
    /* The blitter doesn't support doing any format conversions.  We do also
     * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index 6f5070a7956..7f6db9ddc65 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -335,7 +335,7 @@ intel_nop_alloc_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
  * \param num_samples must be quantized.
  */
 struct intel_renderbuffer *
-intel_create_renderbuffer(gl_format format, unsigned num_samples)
+intel_create_renderbuffer(mesa_format format, unsigned num_samples)
 {
    struct intel_renderbuffer *irb;
    struct gl_renderbuffer *rb;
@@ -373,7 +373,7 @@ intel_create_renderbuffer(gl_format format, unsigned num_samples)
  * \param num_samples must be quantized.
  */
 struct intel_renderbuffer *
-intel_create_private_renderbuffer(gl_format format, unsigned num_samples)
+intel_create_private_renderbuffer(mesa_format format, unsigned num_samples)
 {
    struct intel_renderbuffer *irb;
 
@@ -739,8 +739,8 @@ intel_blit_framebuffer_with_blitter(struct gl_context *ctx,
             return mask;
          }
 
-         gl_format src_format = _mesa_get_srgb_format_linear(src_rb->Format);
-         gl_format dst_format = _mesa_get_srgb_format_linear(dst_rb->Format);
+         mesa_format src_format = _mesa_get_srgb_format_linear(src_rb->Format);
+         mesa_format dst_format = _mesa_get_srgb_format_linear(dst_rb->Format);
          if (src_format != dst_format) {
             perf_debug("glBlitFramebuffer(): unsupported blit from %s to %s.  "
                        "Falling back to software rendering.\n",
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.h b/src/mesa/drivers/dri/i965/intel_fbo.h
index 67f64d365ee..45e2cd89d9e 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.h
+++ b/src/mesa/drivers/dri/i965/intel_fbo.h
@@ -125,22 +125,22 @@ intel_get_renderbuffer(struct gl_framebuffer *fb, gl_buffer_index attIndex)
 }
 
 
-static inline gl_format
+static inline mesa_format
 intel_rb_format(const struct intel_renderbuffer *rb)
 {
    return rb->Base.Base.Format;
 }
 
 extern struct intel_renderbuffer *
-intel_create_renderbuffer(gl_format format, unsigned num_samples);
+intel_create_renderbuffer(mesa_format format, unsigned num_samples);
 
 struct intel_renderbuffer *
-intel_create_private_renderbuffer(gl_format format, unsigned num_samples);
+intel_create_private_renderbuffer(mesa_format format, unsigned num_samples);
 
 struct gl_renderbuffer*
 intel_create_wrapped_renderbuffer(struct gl_context * ctx,
 				  int width, int height,
-				  gl_format format);
+				  mesa_format format);
 
 extern void
 intel_fbo_init(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index c2901decf59..cadf622e587 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -70,7 +70,7 @@ target_to_target(GLenum target)
  * created, based on the chip generation and the surface type.
  */
 static enum intel_msaa_layout
-compute_msaa_layout(struct brw_context *brw, gl_format format, GLenum target)
+compute_msaa_layout(struct brw_context *brw, mesa_format format, GLenum target)
 {
    /* Prior to Gen7, all MSAA surfaces used IMS layout. */
    if (brw->gen < 7)
@@ -225,7 +225,7 @@ intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
 struct intel_mipmap_tree *
 intel_miptree_create_layout(struct brw_context *brw,
                             GLenum target,
-                            gl_format format,
+                            mesa_format format,
                             GLuint first_level,
                             GLuint last_level,
                             GLuint width0,
@@ -391,7 +391,7 @@ intel_miptree_create_layout(struct brw_context *brw,
  */
 static uint32_t
 intel_miptree_choose_tiling(struct brw_context *brw,
-                            gl_format format,
+                            mesa_format format,
                             uint32_t width0,
                             uint32_t num_samples,
                             enum intel_miptree_tiling_mode requested,
@@ -486,7 +486,7 @@ intel_miptree_choose_tiling(struct brw_context *brw,
 struct intel_mipmap_tree *
 intel_miptree_create(struct brw_context *brw,
 		     GLenum target,
-		     gl_format format,
+		     mesa_format format,
 		     GLuint first_level,
 		     GLuint last_level,
 		     GLuint width0,
@@ -497,8 +497,8 @@ intel_miptree_create(struct brw_context *brw,
                      enum intel_miptree_tiling_mode requested_tiling)
 {
    struct intel_mipmap_tree *mt;
-   gl_format tex_format = format;
-   gl_format etc_format = MESA_FORMAT_NONE;
+   mesa_format tex_format = format;
+   mesa_format etc_format = MESA_FORMAT_NONE;
    GLuint total_width, total_height;
 
    if (brw->gen < 8 && !brw->is_baytrail) {
@@ -618,7 +618,7 @@ intel_miptree_create(struct brw_context *brw,
 struct intel_mipmap_tree *
 intel_miptree_create_for_bo(struct brw_context *brw,
                             drm_intel_bo *bo,
-                            gl_format format,
+                            mesa_format format,
                             uint32_t offset,
                             uint32_t width,
                             uint32_t height,
@@ -677,7 +677,7 @@ intel_miptree_create_for_bo(struct brw_context *brw,
 struct intel_mipmap_tree*
 intel_miptree_create_for_dri2_buffer(struct brw_context *brw,
                                      unsigned dri_attachment,
-                                     gl_format format,
+                                     mesa_format format,
                                      uint32_t num_samples,
                                      struct intel_region *region)
 {
@@ -748,7 +748,7 @@ intel_miptree_create_for_dri2_buffer(struct brw_context *brw,
 struct intel_mipmap_tree*
 intel_miptree_create_for_image_buffer(struct brw_context *intel,
                                       enum __DRIimageBufferMask buffer_type,
-                                      gl_format format,
+                                      mesa_format format,
                                       uint32_t num_samples,
                                       struct intel_region *region)
 {
@@ -805,7 +805,7 @@ intel_miptree_create_for_image_buffer(struct brw_context *intel,
 
 struct intel_mipmap_tree*
 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
-                                      gl_format format,
+                                      mesa_format format,
                                       uint32_t width,
                                       uint32_t height,
                                       uint32_t num_samples)
@@ -917,7 +917,7 @@ intel_miptree_match_image(struct intel_mipmap_tree *mt,
     */
    assert(target_to_target(image->TexObject->Target) == mt->target);
 
-   gl_format mt_format = mt->format;
+   mesa_format mt_format = mt->format;
    if (mt->format == MESA_FORMAT_X8_Z24 && mt->stencil_mt)
       mt_format = MESA_FORMAT_S8_Z24;
    if (mt->format == MESA_FORMAT_Z32_FLOAT && mt->stencil_mt)
@@ -1118,7 +1118,7 @@ intel_miptree_copy_slice(struct brw_context *brw,
 			 int depth)
 
 {
-   gl_format format = src_mt->format;
+   mesa_format format = src_mt->format;
    uint32_t width = src_mt->level[level].width;
    uint32_t height = src_mt->level[level].height;
    int slice;
@@ -1215,7 +1215,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
     * accessing this miptree using MCS-specific hardware mechanisms, which
     * infer the correct format based on num_samples.
     */
-   gl_format format;
+   mesa_format format;
    switch (num_samples) {
    case 4:
       /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
@@ -1284,7 +1284,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
     * we'll need to scale the height down by the block height and then a
     * further factor of 8.
     */
-   const gl_format format = MESA_FORMAT_R_UINT32;
+   const mesa_format format = MESA_FORMAT_R_UINT32;
    unsigned block_width_px;
    unsigned block_height;
    intel_get_non_msrt_mcs_alignment(brw, mt, &block_width_px, &block_height);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 69d5b0a22c0..722e346c661 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -285,10 +285,10 @@ struct intel_mipmap_tree
     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
     * formats if the hardware lacks support for ETC1/ETC2. See @ref wraps_etc.
     */
-   gl_format format;
+   mesa_format format;
 
    /** This variable stores the value of ETC compressed texture format */
-   gl_format etc_format;
+   mesa_format etc_format;
 
    /**
     * The X offset of each image in the miptree must be aligned to this.
@@ -497,7 +497,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
 
 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
                                                GLenum target,
-					       gl_format format,
+					       mesa_format format,
                                                GLuint first_level,
                                                GLuint last_level,
                                                GLuint width0,
@@ -510,7 +510,7 @@ struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 struct intel_mipmap_tree *
 intel_miptree_create_layout(struct brw_context *brw,
                             GLenum target,
-                            gl_format format,
+                            mesa_format format,
                             GLuint first_level,
                             GLuint last_level,
                             GLuint width0,
@@ -522,7 +522,7 @@ intel_miptree_create_layout(struct brw_context *brw,
 struct intel_mipmap_tree *
 intel_miptree_create_for_bo(struct brw_context *brw,
                             drm_intel_bo *bo,
-                            gl_format format,
+                            mesa_format format,
                             uint32_t offset,
                             uint32_t width,
                             uint32_t height,
@@ -532,14 +532,14 @@ intel_miptree_create_for_bo(struct brw_context *brw,
 struct intel_mipmap_tree*
 intel_miptree_create_for_dri2_buffer(struct brw_context *brw,
                                      unsigned dri_attachment,
-                                     gl_format format,
+                                     mesa_format format,
                                      uint32_t num_samples,
                                      struct intel_region *region);
 
 struct intel_mipmap_tree*
 intel_miptree_create_for_image_buffer(struct brw_context *intel,
                                      enum __DRIimageBufferMask buffer_type,
-                                     gl_format format,
+                                     mesa_format format,
                                      uint32_t num_samples,
                                      struct intel_region *region);
 
@@ -552,7 +552,7 @@ intel_miptree_create_for_image_buffer(struct brw_context *intel,
  */
 struct intel_mipmap_tree*
 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
-                                      gl_format format,
+                                      mesa_format format,
                                       uint32_t width,
                                       uint32_t height,
                                       uint32_t num_samples);
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 86eabd04e2a..f5b8aa57b0a 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -962,7 +962,7 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
 {
    struct intel_renderbuffer *rb;
    struct intel_screen *screen = (struct intel_screen*) driScrnPriv->driverPrivate;
-   gl_format rgbFormat;
+   mesa_format rgbFormat;
    unsigned num_samples = intel_quantize_num_samples(screen, mesaVis->samples);
    struct gl_framebuffer *fb;
 
@@ -1124,7 +1124,7 @@ intel_supported_msaa_modes(const struct intel_screen  *screen)
 static __DRIconfig**
 intel_screen_make_configs(__DRIscreen *dri_screen)
 {
-   static const gl_format formats[] = {
+   static const mesa_format formats[] = {
       MESA_FORMAT_RGB565,
       MESA_FORMAT_ARGB8888
    };
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index cc50f84ea32..b774efe820e 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -211,7 +211,7 @@ intel_set_texture_image_region(struct gl_context *ctx,
 			       struct intel_region *region,
 			       GLenum target,
 			       GLenum internalFormat,
-			       gl_format format,
+			       mesa_format format,
                                uint32_t offset,
                                GLuint width,
                                GLuint height,
@@ -278,7 +278,7 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
    struct gl_texture_object *texObj;
    struct gl_texture_image *texImage;
    int level = 0, internalFormat = 0;
-   gl_format texFormat = MESA_FORMAT_NONE;
+   mesa_format texFormat = MESA_FORMAT_NONE;
 
    texObj = _mesa_get_current_tex_object(ctx, target);
    intelObj = intel_texture_object(texObj);
diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
index c7f145308d9..f1de6c96bfd 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
@@ -628,7 +628,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
     * the function.
     */
    DBG("%s: level=%d offset=(%d,%d) (w,h)=(%d,%d) format=0x%x type=0x%x "
-       "gl_format=0x%x tiling=%d "
+       "mesa_format=0x%x tiling=%d "
        "packing=(alignment=%d row_length=%d skip_pixels=%d skip_rows=%d) "
        "for_glTexImage=%d\n",
        __FUNCTION__, texImage->Level, xoffset, yoffset, width, height,