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path: root/src/mesa/drivers/dri/i965/intel_batchbuffer.c
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* i965: Rename intelScreen to screen.Kenneth Graunke2016-09-201-3/+3
* i965: Rename __DRIScreen pointers to "dri_screen".Kenneth Graunke2016-09-201-2/+2
* i965: Roll intel_reg.h into brw_defines.hJason Ekstrand2016-08-191-1/+0
* i965: Enable GL_KHR_robustnessKristian Høgsberg Kristensen2016-05-251-0/+3
* i965: Send the minimal number of STATE_BASE_ADDRESS packets.Kenneth Graunke2016-05-161-0/+1
* i965/hsw: Fix brw_store_data_imm*Jordan Justen2016-05-091-10/+12
* i965: Add a brw_load_register_reg64 helper.Kenneth Graunke2016-05-091-0/+18
* i965/gen6+: Add load register immediate helper functionsJordan Justen2016-05-041-0/+32
* i965/hsw+: Add support for copying a registerJordan Justen2016-05-041-0/+15
* i965/gen6+: Add support for storing immediate data into a bufferJordan Justen2016-05-041-0/+45
* i965: Add brw_store_register_mem32Jordan Justen2016-05-041-0/+26
* i965: Use offset instead of index in brw_store_register_mem64Jordan Justen2016-05-041-0/+37
* i965: Don't inline intel_batchbuffer_require_space().Matt Turner2016-03-301-0/+26
* i965: Work around L3 state leaks during context switches.Francisco Jerez2015-12-091-0/+7
* i965: Fix typos in licenseIan Romanick2015-09-101-2/+2
* i965: Remove horizontal bars from file header commentsIan Romanick2015-09-101-4/+2
* i965: Enable hardware-generated binding tables on render path.Abdiel Janulgue2015-07-181-0/+4
* i965: Enable resource streamer for the batchbufferAbdiel Janulgue2015-07-181-1/+7
* i965: Optimize batchbuffer macros.Matt Turner2015-07-151-9/+10
* i965: Add and use USED_BATCH macro.Matt Turner2015-07-151-10/+10
* i965: Split batch emission from relocation functions.Matt Turner2015-07-151-18/+12
* i965/hsw: Implement end of batch workaroundBen Widawsky2015-07-091-2/+25
* i965: Move pipecontrol workaround bo to brw_pipe_controlChris Wilson2015-07-081-12/+0
* i965: Transplant PIPE_CONTROL routines to brw_pipe_controlChris Wilson2015-06-241-304/+0
* i956: Add a function to load a 64-bit register from a bufferNeil Roberts2015-05-121-14/+41
* i965/state: Don't use brw->state.dirty.brwJordan Justen2015-03-311-2/+2
* i965: Defer the throttle until we submit new commandsChris Wilson2015-03-181-0/+44
* i965: Throttle to the previous frameChris Wilson2015-03-181-3/+4
* i965: Rename some PIPE_CONTROL flagsBen Widawsky2015-03-021-4/+4
* i965: Remove hand-rolled memcpy implementation.Matt Turner2015-03-021-1/+1
* i965: Do Sandybridge workaround flushes before each primitive.Kenneth Graunke2015-02-171-12/+0
* i965: Fix up too-wide commentKristian Høgsberg2015-01-161-4/+3
* i965: Implement WaCsStallAtEveryFourthPipecontrol on IVB/BYT.Kenneth Graunke2015-01-041-0/+32
* i965/skl: Emit depth stall workaround for gen9 as wellDamien Lespiau2014-12-081-1/+1
* i965/skl: Implement workaround for VF Invalidate issueJordan Justen2014-11-031-0/+9
* Revert 5 i965 patches: 8e27a4d2, 373143ed, c5bdf9be, 6f56e142, 88e3d404Jordan Justen2014-09-041-2/+2
* i965: Create a macro for setting a dirty bit.Paul Berry2014-09-011-2/+2
* i965: Drop the memcmp for finding duplicated CURBE uploads.Eric Anholt2014-07-021-5/+0
* i965: Reuse intel_upload.c for gen4/5 constant buffers.Eric Anholt2014-07-021-1/+0
* i965: Make batch dumping go to stderr, too.Eric Anholt2014-05-021-0/+1
* i965: Drop some more dead code from the old CACHED_BATCH feature.Eric Anholt2014-03-181-27/+0
* i965: Fix render-to-texture in non-FinishRenderTexture cases.Eric Anholt2014-03-061-0/+4
* i965: Only emit VS state pipe control workaround on IVB and BYT.Kenneth Graunke2014-02-271-1/+1
* i965: Implement a CS stall workaround on Broadwell.Kenneth Graunke2014-02-201-0/+36
* i965: Implement a brw_load_register_mem helper function.Kenneth Graunke2014-02-071-0/+25
* i965: Bump generation assertions on workaround flushes.Kenneth Graunke2014-01-311-2/+2
* i965: Update PIPE_CONTROL packet lengths for Broadwell.Kenneth Graunke2014-01-201-2/+20
* i965: Create a helper function for emitting PIPE_CONTROL writes.Kenneth Graunke2014-01-201-38/+50
* i965: Use full-length PIPE_CONTROL packets for workaround writes.Kenneth Graunke2014-01-201-6/+9
* i965: Emit full-length PIPE_CONTROLs for (non-write) flushes.Kenneth Graunke2014-01-201-2/+3
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