diff options
author | Kenneth Graunke <[email protected]> | 2016-04-27 09:35:03 -0700 |
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committer | Kenneth Graunke <[email protected]> | 2016-05-16 00:11:51 -0700 |
commit | b6f250d7f2f704c8681aaa2a158d1a39851b8494 (patch) | |
tree | efe2c6e0933c9100260566bea5903aed4516102b /src/mesa/drivers/dri/i965/intel_batchbuffer.c | |
parent | 97179c606c998b4f6810b4dc1c5007c848cda4ee (diff) |
i965: Send the minimal number of STATE_BASE_ADDRESS packets.
STATE_BASE_ADDRESS stalls the whole pipeline, and the documentation
cautions us to emit it as little as possible for better performance.
We recently put some hacks in BLORP to try and avoid emitting it
if it was already set correctly. However, this wasn't quite minimal:
if BLORP is the first operation (i.e. glClear()), then it would emit
it, and subsequent draw calls would emit it again.
This caused a small drop in performance in GPUTest Triangle when
switching from Meta to BLORP.
Unlike most packets, STATE_BASE_ADDRESS isn't influenced by GL state:
it needs to be emitted once per batch, before most other commands, or
whenever we change the program cache BO. It's also valid in both the
3D and compute pipelines, which makes it even more unique.
This patch removes it from the atom mechanism and instead directly
calls it as part of every draw, compute dispatch, or BLORP operation.
We introduce a new flag indicating that STATE_BASE_ADDRESS has already
been emitted this batch, and if so, skip doing it again. When we make
a new program cache BO, we simply reset the flag, so the next operation
will emit it again. When we flush/reset the batch, we reset the flag.
This guarantees that we'll emit STATE_BASE_ADDRESS only when we have to.
It's also less code than the old atom mechanism.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_batchbuffer.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_batchbuffer.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index f50b2b473c9..f220311842a 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -73,6 +73,7 @@ intel_batchbuffer_reset(struct brw_context *brw) brw->batch.reserved_space = BATCH_RESERVED; brw->batch.state_batch_offset = brw->batch.bo->size; brw->batch.needs_sol_reset = false; + brw->batch.state_base_address_emitted = false; /* We don't know what ring the new batch will be sent to until we see the * first BEGIN_BATCH or BEGIN_BATCH_BLT. Mark it as unknown. |