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path: root/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
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* i965/vec4: remove the generator hack for dual instanced GSIago Toral Quiroga2016-08-291-31/+0
* i965/eu: Take into account the target cache argument in brw_set_dp_read_message.Francisco Jerez2016-08-251-2/+5
* i965/vec4: Print spills:fills.Matt Turner2016-08-191-7/+11
* i965: Use LZD to implement nir_op_ufind_msbIan Romanick2016-07-191-0/+3
* i965: enable the emission of the DIM instructionSamuel Iglesias Gonsálvez2016-07-141-0/+7
* i965/ir: Make BROADCAST emit an unmasked single-channel move.Francisco Jerez2016-05-271-0/+1
* i965: Fix undefined df bits in brw_reg comparisons.Kenneth Graunke2016-05-141-1/+1
* i965/vec4: Add support for SHADER_OPCODE_MOV_INDIRECTJason Ekstrand2016-04-151-0/+67
* i965/vec4/tcs: Set conditional mod on TCS_OPCODE_SRC0_010_IS_ZERO.Matt Turner2016-03-301-1/+0
* i965/vec4/gen6: fix exec_size for MOV with a width of 4 in generate_gs_ff_sync()Samuel Iglesias Gonsalvez2016-03-171-1/+3
* i965/vec4/gen6: fix exec_size for instructions with destination width of 4Samuel Iglesias Gonsalvez2016-03-171-0/+6
* i965/vec4/gen6: fix exec_size for instructions with width of 4 in generate_gs...Samuel Iglesias Gonsalvez2016-03-171-0/+3
* i965/vec4: Plumb separate surfaces and samplers through from NIRJason Ekstrand2016-02-091-1/+1
* i965/vec4: Separate the sampler from the surface in generate_texJason Ekstrand2016-02-091-5/+13
* i965: Explicitly write the "TR DS Cache Disable" bit at TCS EOT.Kenneth Graunke2016-02-091-1/+4
* i965: Drop extra newline from shader compile messages.Matt Turner2016-01-131-1/+1
* glsl: Move _mesa_shader_stage_to_string/abbrev to shader_enums.cKristian Høgsberg Kristensen2016-01-081-1/+0
* i965: Don't set interleave or complete on TCS EOT message.Kenneth Graunke2015-12-281-2/+34
* i965: Relase input URB Handles on Gen7/7.5 when TCS threads finish.Kenneth Graunke2015-12-281-0/+46
* i965: Use proper TCS barrier ID bits for Ivybridge/Baytrail.Kenneth Graunke2015-12-281-4/+6
* i965: Use proper TCS Instance ID bits for Ivybridge/Baytrail.Kenneth Graunke2015-12-281-2/+5
* i965: Port tessellation evaluation shaders to vec4 mode.Kenneth Graunke2015-12-281-0/+61
* i965: Add tessellation control shaders.Kenneth Graunke2015-12-221-0/+247
* i965/vec4: Use byte offsets for UBO pulls on Sandy BridgeJason Ekstrand2015-12-071-2/+15
* i965/gen9+: Switch thread scratch space to non-coherent stateless access.Francisco Jerez2015-11-261-2/+2
* i965: Clean up #includes in the compiler.Matt Turner2015-11-241-0/+1
* i965: Push down inclusion of brw_program.h.Matt Turner2015-11-241-0/+1
* i965: Prevent implicit upcasts to brw_reg.Matt Turner2015-11-241-5/+5
* i965: Remove fixed_hw_reg field from backend_reg.Matt Turner2015-11-131-6/+6
* i965: Make 'dw1' and 'bits' unnamed structures in brw_reg.Matt Turner2015-11-131-18/+23
* i965: Add initial assembly validation pass.Matt Turner2015-11-121-0/+8
* i965: Set annotation_info's mem_ctx.Matt Turner2015-11-121-1/+1
* i965/vec4: Do not mark used surfaces in VS_OPCODE_GET_BUFFER_SIZEIago Toral Quiroga2015-11-051-2/+0
* i965/vec4: Do not mark used direct surfaces in VS_OPCODE_PULL_CONSTANT_LOADIago Toral Quiroga2015-11-051-9/+0
* i965/vec4/skl+: Use ld2dms_w instead of ld2dmsNeil Roberts2015-11-051-0/+5
* i965: dump scheduling cycle estimatesConnor Abbott2015-10-301-5/+6
* i965/vec4: Test against BRW_IMMEDIATE_VALUE, not IMM.Matt Turner2015-10-291-1/+1
* i965/vec4: Drop brw_set_default_* before popping insn state.Matt Turner2015-10-291-3/+0
* i965/vec4: Remove unnecessary #includes from the generator.Matt Turner2015-10-291-8/+0
* i965/vec4: Eliminate the vec4_generator class altogether.Kenneth Graunke2015-10-291-284/+180
* i965/vec4: Move vec4_generator class definition into the .cpp file.Kenneth Graunke2015-10-291-0/+110
* i965/vec4: Wrap vec4_generator in a C function.Kenneth Graunke2015-10-291-0/+19
* i965/vec4: Convert src_reg/dst_reg to brw_reg at the end of the visitor.Kenneth Graunke2015-10-291-107/+5
* i965/vec4: Remove gl_program and gl_shader_program from the generatorJason Ekstrand2015-10-191-14/+10
* i965/asm: Explicitly use a nir_instr for IR annotationsJason Ekstrand2015-10-191-1/+1
* i965/gs: Allow src0 immediates in GS_OPCODE_SET_WRITE_OFFSET.Kenneth Graunke2015-09-261-2/+7
* i965: Move GS_THREAD_END mlen calculations out of the generator.Kenneth Graunke2015-09-261-1/+1
* i965/vec4: Implement VS_OPCODE_GET_BUFFER_SIZESamuel Iglesias Gonsalvez2015-09-251-0/+31
* i965: Turn BRW_MAX_MRF into a macro that accepts a hardware generationIago Toral Quiroga2015-09-211-5/+5
* i965: Move MRF register asserts out of brw_reg.hIago Toral Quiroga2015-09-211-0/+2
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