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path: root/src/mesa/drivers/dri/i965/brw_pipe_control.c
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* tree-wide: replace MAYBE_UNUSED with ASSERTEDEric Engestrom2019-07-311-1/+1
* i965: Use genxml for emitting PIPE_CONTROL.Kenneth Graunke2019-03-111-201/+42
* i965: Rename ISP_DIS to INDIRECT_STATE_POINTERS_DISABLE.Kenneth Graunke2019-03-111-1/+1
* i965: avoid 'unused variable' warningsAndrii Simiklit2018-11-141-1/+1
* i965: Remove ring switching entirelyJason Ekstrand2018-05-221-22/+10
* i965: Introduce a "memory zone" concept on BO allocation.Kenneth Graunke2018-05-221-1/+2
* i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROLJason Ekstrand2018-05-091-1/+2
* i965: require pixel scoreboard stall prior to ISP disableLionel Landwerlin2018-05-091-1/+8
* i965: Drop unused alignment parameter from brw_bo_alloc().Kenneth Graunke2018-03-271-1/+1
* i965: Drop PIPE_CONTROL_NO_WRITE from various calls.Kenneth Graunke2018-03-271-1/+1
* i965: Shorten the name of the workaround BO.Kenneth Graunke2018-03-011-3/+1
* i965/gen10: Use CS Stall instead of WriteImmediate.cros-mesa-18.1_pre1-r4-vanillachadv/cros-mesa-18.1_pre1-r4-vanillaRafael Antognolli2018-01-261-6/+4
* i965/gen10: Ignore push constant packets during context restore.Rafael Antognolli2018-01-261-0/+49
* i965: Revert Gen8 aspect of VF PIPE_CONTROL workaround.Kenneth Graunke2017-11-171-1/+5
* i965: Implement another VF cache invalidate workaround on Gen8+.Kenneth Graunke2017-11-161-8/+33
* i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DWAnuj Phogat2017-11-141-2/+5
* i965: Program DWord Length in MI_FLUSH_DWAnuj Phogat2017-11-141-1/+1
* i965/gen10: Use the correct form of | for the RCPFE workaroundJason Ekstrand2017-11-101-2/+2
* i965/gen10: Implement WaForceRCPFEHangWorkaroundAnuj Phogat2017-11-031-0/+23
* i965: Add PIPE_CONTRTOL_DATA_CACHE flush to brw_emit_mi_flush().Kenneth Graunke2017-08-301-0/+1
* i965: drop brw->is_haswell in favor of devinfo->is_haswellLionel Landwerlin2017-08-301-2/+2
* i965: drop brw->gen in favor of devinfo->genLionel Landwerlin2017-08-301-15/+29
* i965: Reduce passing 2x32b of reloc_domains to 2 bitsChris Wilson2017-08-041-8/+4
* i965: Do an end-of-pipe sync after flushesJason Ekstrand2017-06-141-3/+3
* i965: Add an end-of-pipe sync helperTopi Pohjolainen2017-06-141-1/+99
* i965: Unify the two emit_pipe_control functionsJason Ekstrand2017-06-141-73/+64
* i965: Take a uint64_t immediate in emit_pipe_control_writeJason Ekstrand2017-06-141-12/+10
* i965/drm: Rename drm_bacon_bo to brw_bo.Kenneth Graunke2017-04-101-5/+5
* i965/drm: Use our internal libdrm (drm_bacon) rather than the real one.Kenneth Graunke2017-04-101-3/+3
* i965/gen6+: Invalidate constant cache on brw_emit_mi_flush().Francisco Jerez2016-12-141-0/+1
* i965: Remove useless (harmful) assertionBen Widawsky2016-09-281-1/+1
* intel: s/brw_device_info/gen_device_info/Jason Ekstrand2016-09-031-1/+1
* i965: Roll intel_reg.h into brw_defines.hJason Ekstrand2016-08-191-1/+1
* i965: Fix remaining flush vs invalidate race conditions in brw_emit_pipe_cont...Francisco Jerez2016-07-071-0/+18
* i965: Emit SKL VF cache invalidation W/A from brw_emit_pipe_control_flush.Francisco Jerez2016-07-071-9/+10
* i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.Francisco Jerez2016-07-071-10/+11
* i965: Fix brw_render_cache_set_check_flush's PIPE_CONTROLs.Kenneth Graunke2016-03-281-2/+0
* i965: Rename define for the PIPE_CONTROL DC flush bit.Francisco Jerez2016-02-081-1/+1
* i965: Only apply CS stall workaround pre-SKLBen Widawsky2015-12-211-2/+4
* i965/gen8: Don't add workaround bits to PIPE_CONTROL stalls if DC flush is set.Francisco Jerez2015-12-091-1/+3
* i965/gen8+: Skip depth stalls on state changeBen Widawsky2015-09-081-0/+8
* i965: Move pipecontrol workaround bo to brw_pipe_controlChris Wilson2015-07-081-6/+34
* i965: Rename intel_emit* to reflect their new location in brw_pipe_controlChris Wilson2015-06-241-4/+4
* i965: Transplant PIPE_CONTROL routines to brw_pipe_controlChris Wilson2015-06-241-0/+331
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