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path: root/src/intel/compiler/brw_nir.h
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* intel/fs: Add and use a new load_simd_width_intel intrinsicCaio Marcelo de Oliveira Filho2020-05-011-2/+1
* intel/compiler: detect if atomic load store operations are usedTapani Pälli2020-03-161-1/+2
* intel: Implement Gen12 workaround for array textures of size 1Lionel Landwerlin2020-01-261-0/+2
* i965: Reuse the new core glsl_count_dword_slots().Eric Anholt2020-01-141-2/+1
* intel/nir: Plumb devinfo through lower_mem_access_bit_sizesJason Ekstrand2019-11-111-1/+2
* nir: Add alpha_to_coverage lowering passSagar Ghuge2019-10-211-0/+1
* intel/nir: Add a helper for getting BRW_AOP from an intrinsicJason Ekstrand2019-08-211-0/+1
* intel/nir: Add a common nir comparison -> cmod helperJason Ekstrand2019-08-031-0/+1
* i965: Use NIR to lower legacy userclipping.Kenneth Graunke2019-07-241-0/+3
* intel/compiler: Be more conservative about subgroup sizes in GLJason Ekstrand2019-07-241-0/+1
* intel/nir: Make brw_nir_apply_sampler_key more genericJason Ekstrand2019-07-241-4/+4
* intel/nir: Take nir_shader*s in brw_nir_link_shadersJason Ekstrand2019-06-051-1/+1
* intel/nir: Stop returning the shader from helpersJason Ekstrand2019-06-051-14/+14
* anv: Use bindless handles for imagesJason Ekstrand2019-04-191-0/+2
* intel/compiler: add a NIR pass to lower conversionsIago Toral Quiroga2019-04-181-0/+2
* nir/i965/freedreno/vc4: add a bindless bool to type size functionsTimothy Arceri2019-04-121-7/+7
* nir/lower_doubles: Inline functions directly in lower_doublesJason Ekstrand2019-03-061-1/+2
* intel/compiler: Lower SSBO and shared loads/stores in NIRJason Ekstrand2018-11-151-0/+2
* intel/compiler: Export TCS passthrough creationCaio Marcelo de Oliveira Filho2018-09-251-0/+5
* intel/compiler: rename brw_nir_lower_glsl_imagesAlejandro Piñeiro2018-09-051-2/+2
* anv,i965: Lower away image derefs in the driverJason Ekstrand2018-08-291-0/+5
* intel/compiler: Do image load/store lowering to NIRJason Ekstrand2018-08-291-0/+3
* intel/nir: Enable nir_opt_find_array_copiesJason Ekstrand2018-08-231-1/+2
* i965: Combine both gl_PatchVerticesIn lowering passes.Kenneth Graunke2018-07-261-2/+0
* intel/compiler: Account for built-in uniforms in analyze_ubo_rangesJason Ekstrand2018-07-231-0/+1
* intel/compiler: Silence unused parameter warnings brw_nir.cIan Romanick2018-07-021-1/+1
* i965: remove unused brw_nir_lower_cs_shared()Timothy Arceri2018-02-071-1/+0
* i965/nir: add a helper to lower gl_PatchVerticesIn to a uniformIago Toral Quiroga2018-01-101-0/+2
* i965: Drop support for the legacy SNORM -> Float equation.Kenneth Graunke2018-01-021-2/+0
* intel/nir: Break the linking code into a helper in brw_nir.cJason Ekstrand2017-11-081-0/+4
* intel/cs: Push subgroup ID instead of base thread IDJason Ekstrand2017-11-071-1/+2
* intel/cs: Rework the way thread local ID is handledJason Ekstrand2017-11-071-2/+1
* intel: Allocate prog_data::[pull_]param deeper inside the compilerJason Ekstrand2017-10-121-2/+3
* intel/compiler: Make brw_nir_lower_intrinsics compute-specificJason Ekstrand2017-10-121-2/+2
* i965/nir: export nir_optimizeTimothy Arceri2017-09-261-0/+4
* i965: Select ranges of UBO data to be uploaded as push constants.Kenneth Graunke2017-07-131-0/+4
* i965/vec4: Use NIR to do GS input remappingJason Ekstrand2017-05-091-1/+1
* i965/vec4: Use NIR remapping for VS attributesJason Ekstrand2017-05-091-1/+0
* intel/compiler: consistently use ifndef guards over pragma onceEmil Velikov2017-03-221-1/+4
* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-131-0/+154
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