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path: root/src/intel/compiler/brw_inst.h
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* intel/compiler: Fix array bounds warning on GCC 10.Timur Kristóf2020-01-221-0/+2
* intel/compiler: Add instruction compaction support on Gen12Matt Turner2019-10-301-0/+12
* intel/fs/gen11+: Fix CS_OPCODE_CS_TERMINATE codegen.Francisco Jerez2019-10-111-2/+2
* intel/eu/gen12: Implement immediate 64 bit constant encoding.Sagar Ghuge2019-10-111-2/+13
* intel/eu/gen12: Implement compact instruction binary encoding.Francisco Jerez2019-10-111-39/+49
* intel/eu/gen12: Implement indirect region binary encoding.Francisco Jerez2019-10-111-8/+15
* intel/eu/gen12: Implement SEND instruction binary encoding.Francisco Jerez2019-10-111-69/+135
* intel/eu/gen12: Implement control flow instruction binary encoding.Francisco Jerez2019-10-111-0/+6
* intel/eu/gen12: Implement three-source instruction binary encoding.Francisco Jerez2019-10-111-67/+85
* intel/eu/gen12: Implement basic instruction binary encoding.Francisco Jerez2019-10-111-47/+51
* intel/eu/gen12: Add sanity-check asserts to brw_inst_bits() and brw_inst_set_...Francisco Jerez2019-10-111-0/+2
* intel/eu/gen12: Extend brw_inst.h macros for Gen12 support.Francisco Jerez2019-10-111-202/+346
* intel/eu: Encode and decode native instruction opcodes from/to IR opcodes.Francisco Jerez2019-10-111-4/+4
* intel/eu: Split brw_inst ex_desc accessors for SEND(C) vs. SENDS(C).Francisco Jerez2019-10-111-27/+41
* tree-wide: replace MAYBE_UNUSED with ASSERTEDEric Engestrom2019-07-311-5/+5
* intel/compiler: add instruction setters for Src1Type and Src2Type.Iago Toral Quiroga2019-04-181-0/+2
* intel/eu: Add support for the SENDS[C] messagesJason Ekstrand2019-01-291-12/+45
* intel/inst: Fix the ia16_addr_imm helpersJason Ekstrand2019-01-291-4/+5
* intel/eu: Use GET_BITS in brw_inst_set_send_ex_descJason Ekstrand2019-01-291-5/+5
* intel/compiler: Expand untyped atomic message type field by a bitIan Romanick2018-08-221-1/+1
* intel/eu: Add brw_inst.h helpers for the SEND(C) descriptor and extended desc...Francisco Jerez2018-07-091-0/+78
* intel/compiler/icl: Clear "null render target" bit in extended message descri...Jason Ekstrand2018-03-221-0/+3
* intel: Split gen_device_info out into libintel_devJordan Justen2018-03-051-1/+1
* i965: Silence warnings about mixing enum and non-enum in conditionalIan Romanick2018-03-021-1/+1
* intel/compiler: Silence unused parameter warnings in release buildsIan Romanick2018-03-021-5/+6
* i965: Add align1 ternary instruction-word supportMatt Turner2017-10-201-0/+108
* i965: Add align1 ternary instruction support to conversion functionsMatt Turner2017-10-201-2/+2
* i965: Add functions to abstract access to 3src register typesMatt Turner2017-10-201-0/+21
* i965: Rename brw_inst's functions that access the 3src register typeMatt Turner2017-10-201-2/+2
* i965: Rename brw_inst 3src functions in preparation for align1Matt Turner2017-10-201-27/+27
* i965: Optimize reading the destination typeMatt Turner2017-08-211-1/+3
* i965: Add functions to abstract access to register typesMatt Turner2017-08-211-0/+28
* i965: Rename brw_inst's functions that access the register typeMatt Turner2017-08-211-3/+3
* i965: Add support for disassembling 64-bit integer immediatesMatt Turner2017-08-211-0/+7
* tree-wide: remove trailing backslashEric Engestrom2017-06-071-1/+1
* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-131-0/+866
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