intel/eu/gen12: Implement basic instruction binary encoding.

Reviewed-by: Jordan Justen <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>

1 files changed, 51 insertions, 47 deletions

diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h
index 5a1e5cfba72..9893e5d903e 100644
--- a/src/intel/compiler/brw_inst.h
+++ b/src/intel/compiler/brw_inst.h
@@ -240,81 +240,85 @@ brw_inst_##name(const struct gen_device_info *devinfo,        \
       return brw_inst_bits(inst, hi4, lo4);                   \
 }
 
-F(src1_vstride,        /* 4+ */ 120, 117, /* 12+ */ -1, -1)
-F(src1_width,          /* 4+ */ 116, 114, /* 12+ */ -1, -1)
+F(src1_vstride,        /* 4+ */ 120, 117, /* 12+ */ 119, 116)
+F(src1_width,          /* 4+ */ 116, 114, /* 12+ */ 115, 113)
 F(src1_da16_swiz_w,    /* 4+ */ 115, 114, /* 12+ */ -1, -1)
 F(src1_da16_swiz_z,    /* 4+ */ 113, 112, /* 12+ */ -1, -1)
-F(src1_hstride,        /* 4+ */ 113, 112, /* 12+ */ -1, -1)
-F(src1_address_mode,   /* 4+ */ 111, 111, /* 12+ */ -1, -1)
+F(src1_hstride,        /* 4+ */ 113, 112, /* 12+ */ 97, 96)
+F(src1_address_mode,   /* 4+ */ 111, 111, /* 12+ */ 112, 112)
 /** Src1.SrcMod @{ */
-F(src1_negate,         /* 4+ */ 110, 110, /* 12+ */ -1, -1)
-F(src1_abs,            /* 4+ */ 109, 109, /* 12+ */ -1, -1)
+F(src1_negate,         /* 4+ */ 110, 110, /* 12+ */ 121, 121)
+F(src1_abs,            /* 4+ */ 109, 109, /* 12+ */ 120, 120)
 /** @} */
-F8(src1_ia_subreg_nr,  /* 4+ */ 108, 106, /* 8+ */ 108, 105, /* 12+ */ -1, -1)
-F(src1_da_reg_nr,      /* 4+ */ 108, 101, /* 12+ */ -1, -1)
+F8(src1_ia_subreg_nr,  /* 4+ */ 108, 106, /* 8+ */  108, 105, /* 12+ */ 111, 108)
+F(src1_da_reg_nr,      /* 4+ */ 108, 101, /* 12+ */ 111, 104)
 F(src1_da16_subreg_nr, /* 4+ */ 100, 100, /* 12+ */ -1, -1)
-F(src1_da1_subreg_nr,  /* 4+ */ 100,  96, /* 12+ */ -1, -1)
+F(src1_da1_subreg_nr,  /* 4+ */ 100,  96, /* 12+ */ 103, 99)
 F(src1_da16_swiz_y,    /* 4+ */ 99,  98,  /* 12+ */ -1, -1)
 F(src1_da16_swiz_x,    /* 4+ */ 97,  96,  /* 12+ */ -1, -1)
-F8(src1_reg_hw_type,   /* 4+ */  46,  44, /* 8+ */  94,  91, /* 12+ */ -1, -1)
-F8(src1_reg_file,      /* 4+ */  43,  42, /* 8+ */  90,  89, /* 12+ */ -1, -1)
-F(src0_vstride,        /* 4+ */ 88,  85,  /* 12+ */ -1, -1)
-F(src0_width,          /* 4+ */ 84,  82,  /* 12+ */ -1, -1)
+F8(src1_reg_hw_type,   /* 4+ */ 46,  44,  /* 8+ */  94,  91, /* 12+ */ 91, 88)
+FI(src1_reg_file,      /* 4+ */ 43,  42,  /* 8+ */  90,  89, /* 12+ */ 47, 98)
+F(src1_is_imm,         /* 4+ */ -1,  -1,  /* 12+ */ 47, 47)
+F(src0_vstride,        /* 4+ */ 88,  85,  /* 12+ */ 87, 84)
+F(src0_width,          /* 4+ */ 84,  82,  /* 12+ */ 83, 81)
 F(src0_da16_swiz_w,    /* 4+ */ 83,  82,  /* 12+ */ -1, -1)
 F(src0_da16_swiz_z,    /* 4+ */ 81,  80,  /* 12+ */ -1, -1)
-F(src0_hstride,        /* 4+ */ 81,  80,  /* 12+ */ -1, -1)
-F(src0_address_mode,   /* 4+ */ 79,  79,  /* 12+ */ -1, -1)
+F(src0_hstride,        /* 4+ */ 81,  80,  /* 12+ */ 65, 64)
+F(src0_address_mode,   /* 4+ */ 79,  79,  /* 12+ */ 80, 80)
 /** Src0.SrcMod @{ */
-F(src0_negate,         /* 4+ */ 78,  78,  /* 12+ */ -1, -1)
-F(src0_abs,            /* 4+ */ 77,  77,  /* 12+ */ -1, -1)
+F(src0_negate,         /* 4+ */ 78,  78,  /* 12+ */ 45, 45)
+F(src0_abs,            /* 4+ */ 77,  77,  /* 12+ */ 44, 44)
 /** @} */
-F8(src0_ia_subreg_nr,  /* 4+ */  76,  74, /* 8+ */  76,  73, /* 12+ */ -1, -1)
-F(src0_da_reg_nr,      /* 4+ */ 76,  69,  /* 12+ */ -1, -1)
-F(src0_da16_subreg_nr  /* 4+ */ 68,  68,  /* 12+ */ -1, -1)
-F(src0_da1_subreg_nr,  /* 4+ */ 68,  64,  /* 12+ */ -1, -1)
+F8(src0_ia_subreg_nr,  /* 4+ */ 76,  74,  /* 8+ */  76,  73, /* 12+ */ 79, 76)
+F(src0_da_reg_nr,      /* 4+ */ 76,  69,  /* 12+ */ 79, 72)
+F(src0_da16_subreg_nr, /* 4+ */ 68,  68,  /* 12+ */ -1, -1)
+F(src0_da1_subreg_nr,  /* 4+ */ 68,  64,  /* 12+ */ 71, 67)
 F(src0_da16_swiz_y,    /* 4+ */ 67,  66,  /* 12+ */ -1, -1)
 F(src0_da16_swiz_x,    /* 4+ */ 65,  64,  /* 12+ */ -1, -1)
-F(dst_address_mode,    /* 4+ */ 63,  63,  /* 12+ */ -1, -1)
-F(dst_hstride,         /* 4+ */ 62,  61,  /* 12+ */ -1, -1)
-F8(dst_ia_subreg_nr,   /* 4+ */  60,  58, /* 8+ */  60,  57, /* 12+ */ -1, -1)
-F(dst_da_reg_nr,       /* 4+ */ 60,  53,  /* 12+ */ -1, -1)
+F(dst_address_mode,    /* 4+ */ 63,  63,  /* 12+ */ 35, 35)
+F(dst_hstride,         /* 4+ */ 62,  61,  /* 12+ */ 49, 48)
+F8(dst_ia_subreg_nr,   /* 4+ */ 60,  58,  /* 8+ */  60,  57, /* 12+ */ 63, 60)
+F(dst_da_reg_nr,       /* 4+ */ 60,  53,  /* 12+ */ 63, 56)
 F(dst_da16_subreg_nr,  /* 4+ */ 52,  52,  /* 12+ */ -1, -1)
-F(dst_da1_subreg_nr,   /* 4+ */ 52,  48,  /* 12+ */ -1, -1)
+F(dst_da1_subreg_nr,   /* 4+ */ 52,  48,  /* 12+ */ 55, 51)
 F(da16_writemask,      /* 4+ */ 51,  48,  /* 12+ */ -1, -1) /* Dst.ChanEn */
-F8(src0_reg_hw_type,   /* 4+ */  41,  39, /* 8+ */  46,  43, /* 12+ */ -1, -1)
-F8(src0_reg_file,      /* 4+ */  38,  37, /* 8+ */  42,  41, /* 12+ */ -1, -1)
-F8(dst_reg_hw_type,    /* 4+ */  36,  34, /* 8+ */  40,  37, /* 12+ */ -1, -1)
-F8(dst_reg_file,       /* 4+ */  33,  32, /* 8+ */  36,  35, /* 12+ */ -1, -1)
-F8(mask_control,       /* 4+ */   9,   9, /* 8+ */  34,  34, /* 12+ */ -1, -1)
+F8(src0_reg_hw_type,   /* 4+ */ 41,  39,  /* 8+ */  46,  43, /* 12+ */ 43, 40)
+FI(src0_reg_file,      /* 4+ */ 38,  37,  /* 8+ */  42,  41, /* 12+ */ 46, 66)
+F(src0_is_imm,         /* 4+ */ -1,  -1,  /* 12+ */ 46, 46)
+F8(dst_reg_hw_type,    /* 4+ */ 36,  34,  /* 8+ */  40,  37, /* 12+ */ 39, 36)
+F8(dst_reg_file,       /* 4+ */ 33,  32,  /* 8+ */  36,  35, /* 12+ */ 50, 50)
+F8(mask_control,       /* 4+ */  9,   9,  /* 8+ */  34,  34, /* 12+ */ 31, 31)
 FF(flag_reg_nr,
    /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
    /* 7: */ 90, 90,
    /* 8: */ 33, 33,
-   /* 12: */ -1, -1)
-F8(flag_subreg_nr,     /* 4+ */  89, 89,  /* 8+ */ 32, 32, /* 12+ */ -1, -1)
-F(saturate,            /* 4+ */ 31,  31,  /* 12+ */ -1, -1)
-F(debug_control,       /* 4+ */ 30,  30,  /* 12+ */ -1, -1)
-F(cmpt_control,        /* 4+ */ 29,  29,  /* 12+ */ -1, -1)
-FC(branch_control,     /* 4+ */ 28,  28,  /* 12+ */ -1, -1, devinfo->gen >= 8)
-FC(acc_wr_control,     /* 4+ */ 28,  28,  /* 12+ */ -1, -1, devinfo->gen >= 6)
+   /* 12: */ 23, 23)
+F8(flag_subreg_nr,     /* 4+ */ 89,  89,  /* 8+ */ 32, 32,   /* 12+ */ 22, 22)
+F(saturate,            /* 4+ */ 31,  31,  /* 12+ */ 34, 34)
+F(debug_control,       /* 4+ */ 30,  30,  /* 12+ */ 30, 30)
+F(cmpt_control,        /* 4+ */ 29,  29,  /* 12+ */ 29, 29)
+FC(branch_control,     /* 4+ */ 28,  28,  /* 12+ */ 33, 33, devinfo->gen >= 8)
+FC(acc_wr_control,     /* 4+ */ 28,  28,  /* 12+ */ 33, 33, devinfo->gen >= 6)
 FC(mask_control_ex,    /* 4+ */ 28,  28,  /* 12+ */ -1, -1, devinfo->is_g4x || devinfo->gen == 5)
-F(cond_modifier,       /* 4+ */ 27,  24,  /* 12+ */ -1, -1)
-FC(math_function,      /* 4+ */ 27,  24,  /* 12+ */ -1, -1, devinfo->gen >= 6)
-F(exec_size,           /* 4+ */ 23,  21,  /* 12+ */ -1, -1)
-F(pred_inv,            /* 4+ */ 20,  20,  /* 12+ */ -1, -1)
-F(pred_control,        /* 4+ */ 19,  16,  /* 12+ */ -1, -1)
+F(cond_modifier,       /* 4+ */ 27,  24,  /* 12+ */ 95, 92)
+FC(math_function,      /* 4+ */ 27,  24,  /* 12+ */ 95, 92, devinfo->gen >= 6)
+F(exec_size,           /* 4+ */ 23,  21,  /* 12+ */ 18, 16)
+F(pred_inv,            /* 4+ */ 20,  20,  /* 12+ */ 28, 28)
+F(pred_control,        /* 4+ */ 19,  16,  /* 12+ */ 27, 24)
 F(thread_control,      /* 4+ */ 15,  14,  /* 12+ */ -1, -1)
-F(qtr_control,         /* 4+ */ 13,  12,  /* 12+ */ -1, -1)
+F(atomic_control,      /* 4+ */ -1,  -1,  /* 12+ */ 32, 32)
+F(qtr_control,         /* 4+ */ 13,  12,  /* 12+ */ 21, 20)
 FF(nib_control,
    /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
    /* 7: */ 47, 47,
    /* 8: */ 11, 11,
-   /* 12: */ -1, -1)
+   /* 12: */ 19, 19)
 F8(no_dd_check,        /* 4+ */  11, 11,  /* 8+ */  10,  10, /* 12+ */ -1, -1)
 F8(no_dd_clear,        /* 4+ */  10, 10,  /* 8+ */   9,   9, /* 12+ */ -1, -1)
-F(access_mode,         /* 4+ */ 8,   8,   /* 12+ */ -1, -1)
+F(swsb,                /* 4+ */  -1, -1,  /* 12+ */ 15,  8)
+FK(access_mode,        /* 4+ */   8,  8,  /* 12+ */ BRW_ALIGN_1)
 /* Bit 7 is Reserved (for future Opcode expansion) */
-F(hw_opcode,           /* 4+ */ 6,   0,   /* 12+ */ -1, -1)
+F(hw_opcode,           /* 4+ */   6,  0,  /* 12+ */ 6,  0)
 
 /**
  * Three-source instructions: