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path: root/src/intel/compiler/brw_disasm.c
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* intel/gen12: Take into account opcode when decoding SWSBCaio Marcelo de Oliveira Filho2020-02-181-1/+2
* intel/disasm: Properly disassemble indirect SENDsJason Ekstrand2020-01-241-3/+16
* intel/compiler: Don't disassemble align1 3-src operands on Gen < 10Matt Turner2020-01-221-0/+12
* intel/disasm: Fix decoding of src0 of SENDSJason Ekstrand2020-01-081-1/+1
* intel/compiler: Refactor disassembly of sources in 3src instructionSagar Ghuge2019-10-211-19/+10
* intel/disasm: Disassemble register file of split SEND sources.Francisco Jerez2019-10-111-1/+4
* intel/disasm: Don't disassemble saturate control on SEND instructions.Francisco Jerez2019-10-111-2/+4
* intel/disasm/gen12: Disassemble Gen12 SEND instructions.Francisco Jerez2019-10-111-4/+18
* intel/disasm/gen12: Disassemble Gen12 SYNC instruction.Francisco Jerez2019-10-111-0/+14
* intel/disasm/gen12: Disassemble three-source instruction source and destinati...Francisco Jerez2019-10-111-13/+32
* intel/disasm/gen12: Fix disassembly of some common instruction controls.Francisco Jerez2019-10-111-4/+9
* intel/disasm/gen12: Disassemble software scoreboard information.Francisco Jerez2019-10-111-0/+16
* intel/eu: Split brw_inst ex_desc accessors for SEND(C) vs. SENDS(C).Francisco Jerez2019-10-111-1/+1
* intel/disasm: Disassemble immediate value properly for dimSagar Ghuge2019-05-071-3/+12
* intel/disasm: Disassemble JIP offset for whileSagar Ghuge2019-05-071-1/+2
* intel/compiler: Print quad value in hex formatSagar Ghuge2019-05-071-1/+1
* intel/fs: Implement nir_intrinsic_global_atomic_*Jason Ekstrand2019-02-011-0/+5
* intel/fs: Implement load/store_global with A64 untyped messagesJason Ekstrand2019-02-011-1/+7
* intel/disasm: Properly disassemble split sendsJason Ekstrand2019-01-291-19/+142
* intel/disasm: Rework SEND decoding to use descriptorsJason Ekstrand2019-01-291-36/+50
* intel/compiler: Always print flag subregister numberSagar Ghuge2018-12-101-7/+6
* intel/compiler: Disassemble GEN6_SFID_DATAPORT_SAMPLER_CACHE as dp_samplerSagar Ghuge2018-11-151-1/+1
* intel/compiler: Print message descriptor as immediate sourceSagar Ghuge2018-10-261-1/+7
* intel/compiler: Print hex representation along with floating point valueSagar Ghuge2018-10-261-3/+9
* intel/compiler: Implement untyped atomic float min, max, and compare-swap dat...Ian Romanick2018-08-221-0/+13
* intel/compiler: Expand untyped atomic message type field by a bitIan Romanick2018-08-221-1/+1
* intel/compiler: Silence unused parameter warningsIan Romanick2018-08-221-3/+0
* i965/fs: Add infrastructure for generating CSEL instructions.Kenneth Graunke2018-03-081-0/+1
* intel/compiler: Add Gen11+ native float typeMatt Turner2018-02-281-0/+7
* intel/compiler: fix 64bit value prints on 32bitGrazvydas Ignotas2018-02-101-2/+2
* i965: Add align1 ternary instruction disassembler supportMatt Turner2017-10-201-64/+288
* i965: Add align1 ternary instruction support to conversion functionsMatt Turner2017-10-201-12/+4
* i965: Rename brw_inst's functions that access the 3src register typeMatt Turner2017-10-201-8/+8
* i965: Rename brw_inst 3src functions in preparation for align1Matt Turner2017-10-201-23/+23
* i965: Print subreg in units of type-size on ternary instructionsMatt Turner2017-10-201-5/+26
* i965: Fix support for disassembling 64-bit integer immediatesMatt Turner2017-10-041-2/+2
* i965: Stop using hardware register types directlyMatt Turner2017-08-211-28/+19
* i965: Add brw_hw_reg_type_to_letters() and use it in brw_disasm.cMatt Turner2017-08-211-39/+33
* i965: Rename brw_inst's functions that access the register typeMatt Turner2017-08-211-11/+11
* i965: Reverse file/type arguments to register type functionsMatt Turner2017-08-211-2/+2
* i965: Add support for disassembling 64-bit integer immediatesMatt Turner2017-08-211-0/+6
* i965: Use separate enums for register vs immediate typesMatt Turner2017-08-211-22/+24
* i965: Fix indentationMatt Turner2017-08-021-6/+6
* intel/compiler: Make brw_disasm take const assemblyJason Ekstrand2017-05-261-10/+10
* i965/disasm: also print nibctrl in IVB for execsize=8Iago Toral Quiroga2017-04-141-3/+3
* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-131-0/+1646
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