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* intel/l3: Return the URB size from devinfo for DG1Rafael Antognolli2020-06-221-0/+4
| | | | | | | | | We don't have any URB size set in the L3 config, since it's a fixed value now. So just return the value that we know from gen_device_info. Reviewed-by: Jordan Justen <[email protected]> Acked-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
* intel/l3: Add DG1 L3 configurationAnuj Phogat2020-06-221-1/+12
| | | | | | | | | | | Reworks: * Jordan: Make DG1 L3 config table empty Signed-off-by: Anuj Phogat <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Acked-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
* intel/l3: Allow platforms to have no l3 configurationsJordan Justen2020-06-221-4/+10
| | | | | | | | | | | | On some gen12 platforms we will use the L3FullWayAllocationEnable and never reconfigure the L3 setup. Suggested-by: Kenneth Graunke <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
* intel/l3: Don't rely on cfg entry URB size being 0 as a sentinalJordan Justen2020-06-221-20/+32
| | | | | | | | | An example entry with URB size being 0 is in the cnl list. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
* meson: use gnu_symbol_visibility argumentDylan Baker2020-06-011-2/+4
| | | | | | | | | | This uses a meson builtin to handle -fvisibility=hidden. This is nice because we don't need to track which languages are used, if C++ is suddenly added meson just does the right thing. Acked-by: Matt Turner <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4740>
* intel/mi-builder: add framework for self modifying batchesLionel Landwerlin2020-05-201-0/+69
| | | | | | | | | | | | v2: Use Jason's idea to store addresses to modify v3: Add ALU flushes (Jason) v4: Remove ALU flush from gen_mi_self_mod_barrier() (Jason) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> (v2) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
* intel: Silence unused parameter warning in __intel_log_use_argsIan Romanick2020-05-141-1/+1
| | | | | | | | | | | | ...in every file that includes intel_log.h. In file included from src/intel/vulkan/anv_private.h:93, from src/intel/vulkan/genX_cmd_buffer.c:27: src/intel/common/intel_log.h: In function ‘__intel_log_use_args’: src/intel/common/intel_log.h:75:34: warning: unused parameter ‘format’ [-Wunused-parameter] Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4994>
* i965: add support for gen 5 pipelined pointers to dumpDave Airlie2020-05-031-1/+168
| | | | | | | I wanted to see inside these, so added support to the dumper. Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4846>
* intel: Move anv_gem_supports_syncobj_wait to common code.Kenneth Graunke2020-05-013-0/+61
| | | | | | | | | This will let me use this in iris. We leave the existing anv function for anv_gem_stubs.c faking, but move the contents to a helper in a new src/intel/common/gen_gem.c file. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3802>
* Fix promotion of floats to doublesAlbert Astals Cid2020-04-181-1/+1
| | | | | | | | | Use the f variants of the math functions if the input parameter is a float, saves converting from float to double and running the double variant of the math function for gaining no precision at all Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3969>
* intel/batch_decoder: Stop printing to stdoutJason Ekstrand2020-04-161-2/+2
| | | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4597>
* intel: drop unused include directoriesEric Engestrom2020-03-281-3/+3
| | | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360>
* meson: inline `inc_common`Eric Engestrom2020-03-281-3/+3
| | | | | | | | | Let's make it clear what includes are being added everywhere, so that they can be cleaned up. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360>
* intel/decoder: don't consider header fields past dword0Lionel Landwerlin2020-03-181-2/+4
| | | | | | | | | v2: use ULL Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Danylo Piliaiev <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4134> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4134>
* intel/isl: Move get_format_encoding function to islSagar Ghuge2020-02-131-73/+2
| | | | | | | | | | | | | | | Move get_format_encoding function to isl and rename to isl_get_aux_map_format_encoding. v2: - Rename isl_get_aux_map_format_encoding to isl_format_get_aux_map_encoding (Jason Ekstrand) Signed-off-by: Sagar Ghuge <[email protected]> Suggested-by: Kenneth Graunke <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3719>
* intel/gen12+: Set way_size_per_bank to 4Anuj Phogat2020-01-311-1/+1
| | | | | | | | This patch fixes the way_size_per_bank for Gen12+ Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Sagar Ghuge<[email protected]>
* intel/gen12+: Reserve 4KB of URB space per bank for Compute EngineAnuj Phogat2020-01-311-1/+19
| | | | | | | | | | | | This patch is required to fix 11K+ vulkan CTS failures we were getting with way_size_per_bank of 4 (see next patch). Thanks to Sagar Ghuge and Jordan Justen for all the hard work of debugging and testing. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Sagar Ghuge<[email protected]>
* intel/tools: Handle strides better when dumping buffersJason Ekstrand2020-01-311-2/+5
| | | | | | | | | | | The old code would only break at stride boundaries if the stride was less than 32B; otherwise it would just break every 32B. This commit makes it break at stride boundaries and 32B boundaries (starting from the last stride). This makes reading large vertex buffers in aubinator much nicer. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642>
* anv: Always fill out the AUX table even if CCS is disabledJason Ekstrand2020-01-302-1/+1
| | | | | | | Cc: "20.0" [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
* intel/common: Return the block size from get_urb_configJason Ekstrand2020-01-302-2/+49
| | | | | | Cc: "20.0" [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
* intel: Take a gen_l3_config in gen_get_urb_configJason Ekstrand2020-01-302-6/+10
| | | | | | | | | | Instead of making each driver pass in the same push constant size and do it's own L3$ config URB size calculation, just make them pass in their L3$ configuration. Cc: "20.0" [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
* intel/mi_builder: Force write completion on Gen12+Jason Ekstrand2020-01-281-0/+3
| | | | | | | | | | | Otherwise, we have no guarantee that the write actually lands before we move on to other things. Doing this on every SDI is probably a bit harsh but it's safe. We should figure out a good way to avoid this when we can. Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>
* intel/aux-map: Factor out some useful helpersJason Ekstrand2020-01-252-28/+91
| | | | | | | | | | | | | | | | | | | | This breaks add_mapping() into three pieces: 1. get_aux_entry() adds AUX-TT pages as needed and returns the L1 entry index, L1 entry address, and L1 entry map. 2. gen_aux_map_format_bits_for_isl_surf() computes the format- specific information that goes in the AUX-TT entry. 3. add_mapping() is a lot dumber function that now just adds the requested mapping with the requested format bits. This lets us break out some additional helpers in the API which we want to use for more direct AUX-TT management in ANV. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3519>
* intel/aux-map: Add some #definesJason Ekstrand2020-01-252-14/+25
| | | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3519>
* intel: Fix aux map alignments on 32-bit builds.Kenneth Graunke2020-01-231-4/+4
| | | | | | | | | | | | | | | ALIGN() brilliantly uses uintptr_t, making it unsafe for use with 64-bit GPU addresses in 32-bit builds of the driver. Use align64() instead, which uses uint64_t. Fixes assertion failures when running any 32-bit program on Tigerlake. Fixes: 2e6a7ced4db ("iris/gen12: Write GFX_AUX_TABLE base address register") Fixes: 0d0290bb3f7 ("intel/common: Add surface to aux map translation table support") Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3507> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3507>
* intel: add mi_builder_test for gen12Eric Engestrom2019-12-111-1/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/decoder: Make get_state_size take a full 64-bit address and a baseKenneth Graunke2019-12-102-11/+20
| | | | | | | | | | | | i965 wants to use an offset from a base because everything is in a single buffer whose address may be relocated, and all base addresses are set to the start of that buffer. iris wants to use a full 64-bit address, because state lives in separate buffers which may be in the shader, surface, and dynamic memory zones, where addresses grow downward from the top of a 4GB zone, So it's very possible for a 32-bit offset to exist relative to multiple bases, leading to the wrong state size.
* intel/aubinator: Decode 3DSTATE_CONSTANT_ALL.Rafael Antognolli2019-12-041-0/+44
| | | | | Acked-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/gen_decoder: Fix unused-but-set-variable warningKai Wasserbäch2019-11-071-2/+2
| | | | | | | | | | | This commit fixes the following warning: ../src/intel/common/gen_decoder.c: In function ‘gen_spec_load_from_path’: ../src/intel/common/gen_decoder.c:741:11: warning: variable ‘len’ set but not used [-Wunused-but-set-variable] 741 | size_t len, filename_len = strlen(path) + 20; | ^~~ Signed-off-by: Kai Wasserbäch <[email protected]> Acked-by: Lionel Landwerlin <[email protected]>
* intel: Enable CCS_E for R24_UNORM_X8_TYPELESS on TGL+Nanley Chery2019-10-281-0/+1
| | | | | | | | While this format isn't listed in BSpec: 53911, other documentation and empirical evidence suggest that it's fine to remap it to R32_FLOAT. I've filed a bug for the BSpec page. Reviewed-by: Kenneth Graunke <[email protected]>
* util: rename list_empty() to list_is_empty()Timothy Arceri2019-10-281-1/+1
| | | | | | | This makes it clear that it's a boolean test and not an action (eg. "empty the list"). Reviewed-by: Eric Engestrom <[email protected]>
* intel/common: Add surface to aux map translation table supportJordan Justen2019-10-283-0/+663
| | | | | | | | | | | | | Reworks: * Add ISL_FORMAT_B8G8R8X8_UNORM_SRGB to get_format_encoding (Nanley) * ralloc_free aux_map_buffer entries in gen_aux_map_finish. (Rafael) * verify_aligned_space => align_and_verify_space (Rafael) * Add mutex to aux-map code. (Rafael, Nanley) * Add gen_aux_map_fill_bos (Ken) * Make gen_aux_map_get_state_num lockless Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/common: Add interface to allocate device buffersJordan Justen2019-10-282-0/+50
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/common: include unistd.h for ioctl() prototype on SolarisAlan Coopersmith2019-10-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes build errors of: In file included from ../src/intel/vulkan/anv_private.h:48, from ../src/intel/vulkan/genX_blorp_exec.c:26: ../src/intel/common/gen_gem.h: In function ‘gen_ioctl’: ../src/intel/common/gen_gem.h:68:15: error: implicit declaration of function ‘ioctl’ [-Werror=implicit-function-declaration] 68 | ret = ioctl(fd, request, arg); | ^~~~~ In file included from ../include/c11/threads_posix.h:35, from ../include/c11/threads.h:66, from ../src/mesa/main/mtypes.h:39, from ../src/intel/compiler/brw_compiler.h:30, from ../src/intel/vulkan/anv_private.h:51, from ../src/intel/vulkan/genX_blorp_exec.c:26: /usr/include/unistd.h: At top level: /usr/include/unistd.h:471:12: error: conflicting types for ‘ioctl’ 471 | extern int ioctl(int, int, ...); | ^~~~~ /usr/include/unistd.h:471:1: note: a parameter list with an ellipsis can’t match an empty parameter name list declaration 471 | extern int ioctl(int, int, ...); | ^~~~~~ In file included from ../src/intel/vulkan/anv_private.h:48, from ../src/intel/vulkan/genX_blorp_exec.c:26: ../src/intel/common/gen_gem.h:68:15: note: previous implicit declaration of ‘ioctl’ was here 68 | ret = ioctl(fd, request, arg); | ^~~~~ Signed-off-by: Alan Coopersmith <[email protected]> Acked-by: Eric Engestrom <[email protected]>
* intel/tools: Decode PS kernels on SNBJason Ekstrand2019-09-061-1/+4
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/tools: Decode 3DSTATE_BINDING_TABLE_POINTERS on SNBJason Ekstrand2019-09-061-0/+15
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/gen12: Add L3 configurationsAnuj Phogat2019-09-061-1/+12
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/l3: Don't assert on gen12 (use gen11 config temporarily)Jordan Justen2019-08-281-0/+1
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Lionel Landwerlin <[email protected]>
* intel/gen_decoder: Decode SLICE_HASH_TABLE.Rafael Antognolli2019-08-121-0/+8
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* meson,i965: Link with android deps when building for android.Bas Nieuwenhuizen2019-08-071-0/+10
| | | | | | | | | | | The DBG marco in brw_blorp.c ends up calling an android log function: error: undefined reference to '__android_log_print' v2: On suggestion from Lionel, hang the Android dependency onto a new libintel_common dependency. Reviewed-by: Lionel Landwerlin <[email protected]>
* meson: drop unused dep_{thread,dl}Eric Engestrom2019-08-031-1/+1
| | | | | | | | Unused as of last commit. Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Eric Anholt <[email protected]> Tested-by: Vinson Lee <[email protected]>
* meson: replace libmesa_util with idep_mesautilEric Engestrom2019-08-031-3/+4
| | | | | | | | | | | This automates the include_directories and dependencies tracking so that all users of libmesa_util don't need to add them manually. Next commit will remove the ones that were only added for that reason. Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Eric Anholt <[email protected]> Tested-by: Vinson Lee <[email protected]>
* intel/device: rename gen_get_device_infoMark Janes2019-08-011-1/+1
| | | | | | | | | | | | | | | | | | Rename the original device info initialization routine so callers don't mistakenly call the wrong one: gen_get_device_info_from_fd: Queries kernel for full device info, including topology details. gen_get_device_info_from_pci_id: Partially initializes device info based on PCI ID lookup, when the kernel is not available. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/common: provide common ioctl routineMark Janes2019-08-011-0/+16
| | | | | | | | | | | i965 links against libdrm for drmIoctl, but anv and iris both re-implement this routine to avoid the dependency. intel/dev also needs an ioctl wrapper, so lets share the same implementation everywhere. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* tree-wide: replace MAYBE_UNUSED with ASSERTEDEric Engestrom2019-07-311-1/+1
| | | | | | Suggested-by: Jason Ekstrand <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/mi: only resolve to a temp register if source isn't in memoryEric Engestrom2019-07-291-1/+1
| | | | | | | | | aka. fix a s/||/&&/ typo Fixes: 74063ee61aadd1371a9b ("intel/mi: Add a new gen_mi_store_if() helper.") Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/mi: Add a unit test for gen_mi_store_if().Kenneth Graunke2019-07-251-0/+43
| | | | | | This tests that predicated stores work. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/mi: Add a new gen_mi_store_if() helper.Kenneth Graunke2019-07-251-0/+53
| | | | | | | This performs predicated MI_STORE_REGISTER_MEM commands, assuming that the condition is already loaded into MI_PREDICATE_DATA. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/mi: Add gen_mi_nz() and gen_mi_z() helpers.Kenneth Graunke2019-07-251-0/+20
| | | | | | These provide comparisons against zero. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/mi: Add a gen_mi_ior() to go with gen_mi_iand()Kenneth Graunke2019-07-251-0/+8
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
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