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path: root/src/gallium/drivers/radeonsi/si_state.c
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* radeonsi: remove tabsMarek Olšák2020-06-261-5/+5
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
* radeonsi: make si_pm4_cmd_begin/end static and simplify all usagesMarek Olšák2020-06-261-4/+2
| | | | | | | There is no longer the confusing trailing si_pm4_cmd_end call. Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
* radeonsi: rename init_config states to cs_preamble statesMarek Olšák2020-06-261-7/+3
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
* radeonsi: don't add the border color buffer into the init_config stateMarek Olšák2020-06-261-1/+0
| | | | | | | We might have to replace init_config for preemption. Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
* ac: add ac_choose_spi_color_formats() to common codeSamuel Pitoiset2020-06-151-109/+6
| | | | | | | | It's similar between RADV and RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5436>
* radeonsi: set BIG_PAGE fields on gfx10.3Marek Olšák2020-06-091-3/+21
| | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
* radeonsi: move L2_CACHE_CONTROL registers into si_emit_framebuffer_stateMarek Olšák2020-06-091-29/+32
| | | | | | | the next commit will set more fields. Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
* radeonsi: implement R9G9B9E5 render target and image store support on gfx10.3Marek Olšák2020-06-091-5/+17
| | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
* radeonsi: honor a user-specified pitch on gfx10.3Marek Olšák2020-06-091-6/+20
| | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
* ac,radeonsi: start adding support for gfx10.3Marek Olšák2020-06-091-5/+12
| | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
* ac,radeonsi: replace == GFX10 with >= GFX10 where it's neededMarek Olšák2020-06-091-2/+3
| | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
* radeonsi: Define gfx10_format in the common header.Bas Nieuwenhuizen2020-06-031-10/+1
| | | | | | | | | | | | | So we don't have to have multiple definitions of the struct when sharing with radv. While at it put the table properly in a C file so we don't have to deal with multiple definitions, and the struct definition isn't in generated source. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5291>
* amd/common,radeonsi: Move gfx10_format_table to common.Bas Nieuwenhuizen2020-06-031-1/+1
| | | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5291>
* radeonsi: add a hack to disable TRUNC_COORD for shadow samplersMarek Olšák2020-06-021-1/+2
| | | | | | | | | | | This fixes dEQP-GLES3.functional.shaders.texture_functions.textureprojlodoffset.sampler2dshadow_vertex. This is probably a dEQP bug. Fixes: d573d1d82524b8a2e5f56938069cabc0f0176a0e Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5209>
* amd: replace SH -> SA (shader array) in commentsMarek Olšák2020-05-261-2/+2
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5184>
* ac/gpu_info: replace num_good_cu_per_sh with min/max_good_cu_per_saMarek Olšák2020-05-261-1/+1
| | | | | | | Perf counters use the new max number. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5184>
* ac: update register and packet definitions for preemptionMarek Olšák2020-05-231-2/+2
| | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
* radeonsi: don't use INDIRECT_BUFFER within IBsMarek Olšák2020-05-231-1/+0
| | | | | | | | It's fragile. If I change the size or alignment, it hangs. Better safe than sorry. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
* radeonsi: use display_dcc_offset for setting displayable_dcc_cb_maskMarek Olšák2020-05-151-1/+1
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
* radeonsi: use vi_dcc_enabled instead of using tex->surface.dcc_offset directlyMarek Olšák2020-05-151-2/+2
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
* radeonsi: Use TRUNC_COORD on samplersJoshua Ashton2020-05-151-0/+3
| | | | | | | | | | | | | | | | The default behaviour (0) is: "round-nearest-even to n.6 and drop fraction when point sampling" whereas the OpenGL spec simply wants us to floor it (1) "truncate when point sampling". See 8.14.2 in the OpenGL spec: https://www.khronos.org/registry/OpenGL/specs/gl/glspec46.core.pdf The Direct3D spec also mandates this (https://microsoft.github.io/DirectX-Specs/d3d/archive/D3D11_3_FunctionalSpec.htm#7.18.7%20Point%20Sample%20Addressing) On WineD3D: This fixes some point-sampling texture precision issues in some Direct3D 9 titles such as Guild Wars 2 and htoL#NiQ: The Firefly Diary that are not present on other vendors. CC: <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3953>
* radeonsi: don't expose 16xAA on chips with 1 RB due to an occlusion query issueMarek Olšák2020-05-151-9/+9
| | | | | | | | Only Stoney and Raven2 are affected. Cc: 20.0 20.1 <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5047>
* gallium: change comments to remove 'state tracker'Marek Olšák2020-05-131-2/+2
| | | | | | | Acked-by: Eric Anholt <[email protected]> Acked-by: Alyssa Rosenzweig <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4902>
* amd: assume HTILE is always rb/pipe_aligned, remove ac_surface.u.gfx9.htileMarek Olšák2020-05-071-2/+2
| | | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>
* amd: assume CMASK is always rb/pipe_aligned, remove ac_surface.u.gfx9.cmaskMarek Olšák2020-05-071-7/+8
| | | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>
* radeonsi: allow tc_compatible_htile to be mutableMarek Olšák2020-05-051-44/+56
| | | | | | | | | Move the relevant code from si_init_depth_surface to si_emit_framebuffer_state, so that it can be changed after a pipe_surface is initialized. Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4866>
* radeonsi/gfx9: always use IMG_DATA_FORMAT_S8_32 for 8-bit stencilMarek Olšák2020-05-051-2/+1
| | | | | | | | I wanna remove dependency on tc_compatible_htile from non-dynamic states. This should be the same as 8_UINT if HTILE is disabled. Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4866>
* ac/surface: add code for gfx10 displayable DCCMarek Olšák2020-04-291-4/+4
| | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4697>
* radeonsi: use pipe_blend_state::max_rt to update fewer blend registersMarek Olšák2020-04-241-3/+7
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4698>
* ac,radeonsi: simplify checking for Navi1x chipsMarek Olšák2020-04-241-2/+2
| | | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4698>
* radeonsi: enable support for AlphaToCoverageDitherControlNVIndrajit Kumar Das2020-04-231-5/+13
| | | | | Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4543>
* radeonsi: switch to 3-spaces stylePierre-Eric Pelloux-Prayer2020-03-301-5155/+4825
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Generated automatically using clang-format and the following config: AlignAfterOpenBracket: true AlignConsecutiveMacros: true AllowAllArgumentsOnNextLine: false AllowShortCaseLabelsOnASingleLine: false AllowShortFunctionsOnASingleLine: false AlwaysBreakAfterReturnType: None BasedOnStyle: LLVM BraceWrapping: AfterControlStatement: false AfterEnum: true AfterFunction: true AfterStruct: false BeforeElse: false SplitEmptyFunction: true BinPackArguments: true BinPackParameters: true BreakBeforeBraces: Custom ColumnLimit: 100 ContinuationIndentWidth: 3 Cpp11BracedListStyle: false Cpp11BracedListStyle: true ForEachMacros: - LIST_FOR_EACH_ENTRY - LIST_FOR_EACH_ENTRY_SAFE - util_dynarray_foreach - nir_foreach_variable - nir_foreach_variable_safe - nir_foreach_register - nir_foreach_register_safe - nir_foreach_use - nir_foreach_use_safe - nir_foreach_if_use - nir_foreach_if_use_safe - nir_foreach_def - nir_foreach_def_safe - nir_foreach_phi_src - nir_foreach_phi_src_safe - nir_foreach_parallel_copy_entry - nir_foreach_instr - nir_foreach_instr_reverse - nir_foreach_instr_safe - nir_foreach_instr_reverse_safe - nir_foreach_function - nir_foreach_block - nir_foreach_block_safe - nir_foreach_block_reverse - nir_foreach_block_reverse_safe - nir_foreach_block_in_cf_node IncludeBlocks: Regroup IncludeCategories: - Regex: '<[[:alnum:].]+>' Priority: 2 - Regex: '.*' Priority: 1 IndentWidth: 3 PenaltyBreakBeforeFirstCallParameter: 1 PenaltyExcessCharacter: 100 SpaceAfterCStyleCast: false SpaceBeforeCpp11BracedList: false SpaceBeforeCtorInitializerColon: false SpacesInContainerLiterals: false Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
* ac: add radeon_info::use_late_alloc to control LATE_ALLOC globallyMarek Olšák2020-03-121-3/+5
| | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>
* radeonsi: set better tessellation tunables on gfx9 and gfx10Marek Olšák2020-03-121-1/+8
| | | | | | | same as PAL Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>
* radeonsi/gfx10: cache metadata in L2 on small chipsMarek Olšák2020-03-121-8/+19
| | | | | | | same as PAL. Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>
* radeonsi: don't update states for the DCC MSAA bug on GFX6-7Marek Olšák2020-02-101-2/+2
| | | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3646> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3646>
* radeonsi: fix the DCC MSAA bug workaroundMarek Olšák2020-02-101-1/+1
| | | | | | Cc: 19.3 20.0 <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3646>
* radeonsi: don't report that multi-plane formats are supportedMarek Olšák2020-02-071-7/+0
| | | | | | | | | Fixes: a554b45d - st/mesa: don't lower YUV when driver supports it natively Closes: #2376 Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3632> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3632>
* radeonsi/gfx10: rewrite late alloc computationMarek Olšák2020-01-201-39/+33
| | | | | | | | - Use conservative late alloc when the number of CUs <= 6. - Move the late alloc GS register to the GS shader state, so that it can be tuned for NGG culling. Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: implement NGG culling for 4x wave32 subgroupsMarek Olšák2020-01-201-0/+1
| | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: move GE_PC_ALLOC setting to shader statesMarek Olšák2020-01-201-13/+0
| | | | | | | | The value is not changed. I just use a different way to compute it. The value will vary with NGG culling. Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: drop the negation from fmask_is_not_identityPierre-Eric Pelloux-Prayer2020-01-151-1/+1
| | | | | | | | | | | This change eases code reading ("fmask_is_identity = true" is clearer than "fmask_is_not_identity = false"). Initialization is not changed so fmask_is_identity is false when a texture is created. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>
* radeonsi: fork tgsi_shader_info and tgsi_tessctrl_infoMarek Olšák2020-01-141-1/+1
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: put up to 5 VBO descriptors into user SGPRsMarek Olšák2020-01-131-3/+14
| | | | | | | | | | | | | | | | | | | | | gfx6-8: 1 VBO descriptor in user SGPRs gfx9-10: 5 VBO descriptors in user SGPRs We no longer pull up to 5 VBO descriptors from GTT when SDMA is disabled. Totals from affected shaders: SGPRS: 1110528 -> 1170528 (5.40 %) VGPRS: 952896 -> 951936 (-0.10 %) Spilled SGPRs: 83 -> 61 (-26.51 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 23766296 -> 22843920 (-3.88 %) bytes LDS: 0 -> 0 (0.00 %) blocks Max Waves: 179344 -> 179344 (0.00 %) Wait states: 0 -> 0 (0.00 %) Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: simplify si_set_vertex_buffersMarek Olšák2020-01-131-7/+8
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: add si_context::num_vertex_elementsMarek Olšák2020-01-131-0/+1
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: rename desc_list_byte_size -> vb_desc_list_alloc_sizeMarek Olšák2020-01-131-1/+1
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* ac/gpu_info: add pc_lines and use it in radeonsiMarek Olšák2020-01-081-1/+1
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: determine accurately if line stippling is enabled for performanceMarek Olšák2020-01-081-3/+4
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: test polygon mode enablement accuratelyMarek Olšák2020-01-081-2/+4
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-15 00:19:28 +0000