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path: root/src/broadcom/compiler/vir_to_qpu.c
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* v3d: Eliminate the TLB and TLBU files.Eric Anholt2019-03-051-12/+0
* v3d: Use ldunif instructions for uniforms.Eric Anholt2019-03-051-25/+0
* v3d: Add support for vir-to-qpu of ldunif instructions to a temp.Eric Anholt2019-03-051-2/+15
* v3d: Switch implicit uniforms over to being any qinst->uniform != ~0.Eric Anholt2019-03-051-6/+2
* v3d: Add a helper function for getting a nop register.Eric Anholt2019-02-181-1/+1
* v3d: Add a note for a potential performance win on multop/umul24.Eric Anholt2018-12-301-0/+4
* v3d: Fix uniform pretty printing assertion failure with branches.Eric Anholt2018-12-291-0/+3
* v3d: Do uniform pretty-printing in the QPU dump.Eric Anholt2018-12-141-1/+47
* v3d: Fix a leak of the disassembled instruction string during debug dumps.Eric Anholt2018-12-071-0/+1
* v3d: Implement a small immediates optimization, based on VC4's.Eric Anholt2018-07-231-9/+7
* v3d: Disable shader-db cycle estimates until we sort out TMU estimates.Eric Anholt2018-07-161-1/+4
* broadcom/vc5: On QPU pack error, dump the instruction and return cleanly.Eric Anholt2018-03-191-1/+7
* broadcom/vc5: Remove no-op MOVs after register allocation.Eric Anholt2018-02-051-1/+60
* broadcom/vc5: Add missing shader-db instruction counting.Eric Anholt2018-02-051-0/+7
* broadcom/vc5: Add support for loading varyings in V3D 4.1.Eric Anholt2018-01-121-7/+0
* broadcom/vc5: Use THRSW to enable multi-threaded shaders.Eric Anholt2018-01-121-3/+1
* broadcom/vc5: Properly schedule the thread-end THRSW.Eric Anholt2018-01-121-6/+0
* broadcom/vc5: Add support for V3Dv4 signal bits.Eric Anholt2018-01-121-1/+8
* nir: Get rid of nir_shader::stageJason Ekstrand2017-10-201-1/+1
* broadcom: Add VC5 NIR compiler.Eric Anholt2017-10-101-0/+359
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