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* radv: Implement determining the has_multiview_view_index key.Bas Nieuwenhuizen2017-08-241-4/+16
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Add multiview clears.Bas Nieuwenhuizen2017-08-243-19/+47
| | | | | | v2: Use for_each_bit. Reviewed-by: Dave Airlie <[email protected]>
* radv: Store multiview info in renderpass.Bas Nieuwenhuizen2017-08-242-1/+27
| | | | Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: Make shader key a struct.Bas Nieuwenhuizen2017-08-243-16/+16
| | | | | | | Some bits can be passed to almost every shader, and I don't like adding 5 variables. Reviewed-by: Dave Airlie <[email protected]>
* radv: Use 0 for the layer id if the vertex shader does not export it.Bas Nieuwenhuizen2017-08-241-3/+4
| | | | | | | To use when we have e.g. input attachments, but there is no layer export in the previous shader and hence no layered rendering. Reviewed-by: Dave Airlie <[email protected]>
* radv/gfx9: don't expose linear depth on vega.Dave Airlie2017-08-241-0/+4
| | | | | | | | This just zeros out the linear flags for gfx9 + depth formats. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: don't degrade tiling mode for small compressed or depth texture.Dave Airlie2017-08-241-6/+10
| | | | | | | | | This is what radeonsi does, so we should do the same, also vega doesn't support linear depth textures anyways. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: only minify image view width/height/depth before gfx9.Dave Airlie2017-08-242-7/+15
| | | | | | | | | | | For gfx9 the addressing for images has changed, so we need to provide the hw with the level0, however we still need to scale for format block differences (so our compressed upload paths still work). Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/image: don't rescale width/height if the format isn't changingDave Airlie2017-08-241-4/+6
| | | | | | | | | If the image view has the same format, we don't need to rescale the w/h. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: cleanup some image view descriptor setup.Dave Airlie2017-08-242-13/+21
| | | | | | | | | | | | Avoid passing the vulkan image creation into the image view descriptor setup. This cleans up the usage of range inside the init, instead using the properly inited values in the image view. This is just a cleanup but some future vega changes will depend on it. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: emit sx_mrt_blend registersDave Airlie2017-08-243-3/+134
| | | | | | | | | | | | | GFX9 needs the SX MRT blend registers programmed, port over the code from radeonsi to workout the values from the blend state, and program the registers on rbplus systems. This fixes lots of: dEQP-VK.pipeline.blend.* Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: bump space check for indexed draw.Dave Airlie2017-08-241-1/+1
| | | | | | | | | | | For the GFX9 packet we need one more dword. Fixes an assert in: dEQP-VK.draw.shader_draw_parameters.base_vertex.draw_indexed Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: fixup db/stencil disable.Dave Airlie2017-08-241-3/+7
| | | | | | | | This fixes disabled Z/stencil. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: fix level count in color register setup.Dave Airlie2017-08-241-1/+1
| | | | | | | | There was an off by one here. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: use total levels in texture descriptorDave Airlie2017-08-241-1/+1
| | | | | | | | | We need to use all the levels when filling out the gfx9 descriptor. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Implement bc optimize.Bas Nieuwenhuizen2017-08-241-0/+3
| | | | | | | | Seems like we actually enabled it already, but did not implement the shader part. With this patch we do. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: disable support for VEGA for now.Dave Airlie2017-08-181-0/+5
| | | | | | | | | I'm working on this, but I'm not sure I'll make 17.2 at this stage, maybe 17.2.1. Cc: "17.2" <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: for fast clear use is_linear flag.Dave Airlie2017-08-161-1/+1
| | | | | | | | The legacy test won't work on gfx9. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: fix tile swizzle handling for gfx9David Airlie2017-08-162-11/+8
| | | | | | | | This sets the tile swizzle up properly for gfx9. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: handle GFX9 opaque metadataDavid Airlie2017-08-161-4/+5
| | | | | | | | port the opaque metadata changes from radeonsi for gfx9. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: emit db_htile_surface reg on gfx9 as wellDavid Airlie2017-08-161-1/+2
| | | | | | | | This is also a GFX9 register. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: remove some leftover gfx6 descriptor setup.Dave Airlie2017-08-161-4/+0
| | | | | | | | | We set this later in the non-gfx9 path, just remove these bits from here. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: fix set predication packet.Dave Airlie2017-08-161-9/+12
| | | | | | | | The predication packet changed format on GFX9, update the driver. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: force cs/ps/l2 flush at end of command stream. (v2)Dave Airlie2017-08-091-1/+4
| | | | | | | | | | | | | | | | | | | | This seems like a workaround, but we don't see the bug on CIK/VI. On SI with the dEQP-VK.memory.pipeline_barrier.host_read_transfer_dst.* tests, when one tests complete, the first flush at the start of the next test causes a VM fault as we've destroyed the VM, but we end up flushing the compute shader then, and it must still be in the process of doing something. Could also be a kernel difference between SI and CIK. v2: hit this with a bigger hammer. This fixes a bunch of hangs in the vk cts with the robustness tests. Fixes: f4e499ec791 ("radv: add initial non-conformant radv vulkan driver") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101334 Acked-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: remove semicolon in if(...);Bas Nieuwenhuizen2017-08-081-1/+1
| | | | | | Trivial. Fixes: a6a6146aa91 "radv: Don't allow fmask swizzling for shareable images."
* radv: Fix decompression on multisampled depth buffersAlex Smith2017-08-072-35/+69
| | | | | | | | | | Need to take the sample count into account in the depth decompress and resummarize pipelines and render pass. Fixes: f4e499ec791 ("radv: add initial non-conformant radv vulkan driver") Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]>
* radv: Don't allow fmask swizzling for shareable images.Bas Nieuwenhuizen2017-08-071-1/+4
| | | | | | | | Also adds an assert because you never know how the winsys changes, and multiprocess format differences are annoying. Fixes: 1e696b962b7 "radv: add separate fmask tile swizzle counter." Reviewed-by: Dave Airlie <[email protected]>
* radv: fix MSAA on SI gpus.Dave Airlie2017-08-071-3/+7
| | | | | | | | | | This ports the workaround from radeonsi, that was missing in radv. This fixes Talos rendering when MSAA is enabled on my Tahiti card. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver) Signed-off-by: Dave Airlie <[email protected]>
* radv: add separate fmask tile swizzle counter.Dave Airlie2017-08-073-3/+11
| | | | | | | | | This mirrors what Marek has done for radeonsi, and uses a separate counter to handle the fmask surface for MSAA MRTs. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Use the correct channel for alpha in resolve srgb conversion.Bas Nieuwenhuizen2017-08-061-1/+1
| | | | | | | | | The argument here is a bitmask, so the old code selected .xy, which got silently truncated to .x when constructing the vec4 from components, instead of using .w. Fixes: 588185eb6b7 "radv/meta: add srgb conversion to end of resolve shader." Reviewed-by: Dave Airlie <[email protected]>
* radv: Only convert linear->srgb in compute resolves.Bas Nieuwenhuizen2017-08-065-79/+54
| | | | | | | | | It justs works with the fragment shader resolve, so no need to do a custom conversion. In fact with SRGB dest, it actually gives wrong results. Fixes: 69136f4e633 "radv/meta: add resolve pass using fragment/vertex shaders" Reviewed-by: Dave Airlie <[email protected]>
* radv: Don't use SRGB format for image stores during resolve.Bas Nieuwenhuizen2017-08-062-1/+24
| | | | | | | | | These seem to store very bogus results. Luckily there is some code that converts srgb->linear already, so just making the descriptor format UNORM should work. Fixes: 588185eb6b7 "radv/meta: add srgb conversion to end of resolve shader." Reviewed-by: Dave Airlie <[email protected]>
* radv: generate the same driver UUID as radeonsiAndres Rodriguez2017-08-062-1/+9
| | | | | | | These need to match for interop compatibility queries. Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radv: generate same device UUID as radeonsiAndres Rodriguez2017-08-061-7/+4
| | | | | | | | | | | This is required for interop use cases. The same device must report identical UUIDs through the GL and Vulkan APIs so that users can identify when it is safe to perform a memory object import. v2: use ac helpers to calculate the uuid Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radv: avoid GPU hangs if someone does a resolve with non-multisample src (v2)Dave Airlie2017-08-051-0/+5
| | | | | | | | | | | | This is a bug in the app, but I'd rather avoid hanging the GPU, esp if someone is running in validation and it takes out their development environment. v2: get it right, reverse the polarity. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: also fix texture image descriptors for mipmap tile swizzleDave Airlie2017-08-041-1/+2
| | | | | | | This fixes the image descriptors for mipmapped tile swizzle Fixes: 2b7e8556 (ac/surface: enable tile swizzle for mipmapped textures) Signed-off-by: Dave Airlie <[email protected]>
* radv: fix tile swizzle regression on mipmaps.Dave Airlie2017-08-041-5/+6
| | | | | | | | | | | When Marek enabled mipmapped swizzle, radv didn't have the code in place to handle it. This fixes the regression. I'll look more into GFX9 once I have a vega card (soon). Fixes: 2b7e8556 (ac/surface: enable tile swizzle for mipmapped textures) Signed-off-by: Dave Airlie <[email protected]>
* ac/surface: increment surf_index only when tile swizzle is allowedMarek Olšák2017-08-041-1/+1
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: remove RADEON_SURF_HAS_TILE_MODE_INDEXMarek Olšák2017-08-042-4/+0
| | | | | | | it's useless Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: move tile_swizzle to ac_surface and document itMarek Olšák2017-08-042-6/+6
| | | | | | | Gfx9 will use it too. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radv: Add suballocation for shaders.Bas Nieuwenhuizen2017-08-035-21/+93
| | | | | | | | | | | | | This reduces the number of BOs that we need for the BO lists during a submission. Currently uses a fairly simple linear search for finding free space, that could eventually be improved to a binary tree, which with some per-node info could make a check for space O(1) and finding it O(log n), in the number of buffers in that slab. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: handle 10-bit format clamping workaround.Dave Airlie2017-08-016-10/+37
| | | | | | | | | | | | | | | This fixes: dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.* for a2r10g10b10 formats as destination on SI/CIK hardware. This adds support to the meta program for emitting 10-bit outputs, and adds 10-bit support to the fragment shader key. It also only does the int8/10 on SI/CIK. Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Don't underflow non-visible VRAM size.Bas Nieuwenhuizen2017-07-311-2/+4
| | | | | | | | | | | | | | In some APU situations the reported visible size can be larger than VRAM size. This properly clamps the value. Surprisingly both CTS and spec seem to allow a heap type with size 0, so this seemed like the easiest option to me. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Fixes: 4ae84efbc5c "radv: Use enum for memory heaps." Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Tested-by: Michel Dänzer <[email protected]>
* ac/nir,radv: move force_persample to ac_shader_info::force_persampleNicolai Hähnle2017-07-312-2/+2
| | | | | | | Avoid accessing radv-specific structures during the meat of NIR-to-LLVM translation. Reviewed-by: Marek Olšák <[email protected]>
* radv: for stencil only set Z tile mode index to same valueDave Airlie2017-07-281-0/+2
| | | | | | | | | | | | On SI this was causing a hang in dEQP-VK.pipeline.render_to_image.core.2d_array.mipmap.r16g16_sint_s8_uint This was due to not handling the tile mode index for depth like I fixed previously for new GPUs. Fixes: 01d0c5a9 (radv: fix stencil regression since new addrlib import) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/winsys: fix padding command stream for SIDave Airlie2017-07-261-4/+6
| | | | | | | | We were adding pad to size after creating the object, so we could submit a CS bigger than the bo created for it. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: rename physical_device->uuid[] to cache_uuid[]Andres Rodriguez2017-07-263-5/+5
| | | | | | | We have a few UUIDs, so lets be more specific. Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radv: only report external semaphore info for opaque fd.Dave Airlie2017-07-251-5/+10
| | | | | | | | | | Until we support sync fd, don't report the info. Fixes CTS dEQP-VK.api.external.semaphore.sync_fd.* from crashing. Fixes: eaa56eab6 (radv: initial support for shared semaphores (v2)) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix buffer views on SI/CIK.Dave Airlie2017-07-241-0/+5
| | | | | | | | | Fixes CTS dEQP-VK.memory.pipeline_barrier.host_write_uniform_texel_buffer.1024 on SI/CIK with radv. Fixes: f4e499ec (radv: add initial non-conformant radv vulkan driver) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: enable sample shadingDave Airlie2017-07-242-2/+4
| | | | | | | This calculates ps_iter_samples from the minSampleShading input Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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