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authorDave Airlie <[email protected]>2017-07-27 04:51:48 +0100
committerDave Airlie <[email protected]>2017-07-28 04:12:32 +0100
commit800d1622096ca52b955bdfc20eb770b80ef15221 (patch)
treec6a50d0be6d8a9a24e3b88353e98e96bd554413e /src/amd/vulkan
parent554aa094406f3f5a935c4adbe77569cc9beb4312 (diff)
radv: for stencil only set Z tile mode index to same value
On SI this was causing a hang in dEQP-VK.pipeline.render_to_image.core.2d_array.mipmap.r16g16_sint_s8_uint This was due to not handling the tile mode index for depth like I fixed previously for new GPUs. Fixes: 01d0c5a9 (radv: fix stencil regression since new addrlib import) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan')
-rw-r--r--src/amd/vulkan/radv_device.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 752d70be4bb..eb2587212c8 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3246,6 +3246,8 @@ radv_initialise_ds_surface(struct radv_device *device,
ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
tile_mode_index = si_tile_mode_index(iview->image, level, true);
ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
+ if (stencil_only)
+ ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
}
ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |