i965/gen10: Remove unnecessary workaround.

In fact, the description of the workaround states that the mask field
doesn't work correctly on gen10, and we need to set it to 0xffff even we
we only want to update a single field:

 "The mask bits are not implemented properly on 3DSTATE_3D_MODE.  Driver
 must always program bits 31:16 of DW1 a value of 0xFFFF.   This means
 if it is only updating 1 field, it must update all the fields to the
 correct value."

So unless we want to change any of the fields of 3DSTATE_3D_MODE,
there's not need to emit. Additionally, it seems this workaround is not
required on gen11. And last but not least, this workaround is not
implemented on iris or anv, and it doesn't seem to be missed there.

So let's just remove the whole thing.

Reviewed-by: Kenneth Graunke <[email protected]>

1 files changed, 0 insertions, 16 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 041bf159d5a..deb4ba5697d 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -124,22 +124,6 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
                               REG_MASK(GEN11_DISABLE_REPACKING_FOR_COMPRESSION));
    }
 
-   if (devinfo->gen == 10 || devinfo->gen == 11) {
-      /* From gen10 workaround table in h/w specs:
-       *
-       *    "On 3DSTATE_3D_MODE, driver must always program bits 31:16 of DW1
-       *     a value of 0xFFFF"
-       *
-       * This means that we end up setting the entire 3D_MODE state. Bits
-       * in this register control things such as slice hashing and we want
-       * the default values of zero at the moment.
-       */
-      BEGIN_BATCH(2);
-      OUT_BATCH(_3DSTATE_3D_MODE  << 16 | (2 - 2));
-      OUT_BATCH(0xFFFF << 16);
-      ADVANCE_BATCH();
-   }
-
    if (devinfo->gen == 9) {
       /* Recommended optimizations for Victim Cache eviction and floating
        * point blending.