diff options
| author | Anuj Phogat <[email protected]> | 2015-05-04 23:10:28 -0700 |
|---|---|---|
| committer | Anuj Phogat <[email protected]> | 2015-06-15 09:07:28 -0700 |
| commit | 278460279b4e089d51a24fb01dc56dc1e88dcb72 (patch) | |
| tree | 664041299f0f139cb0408ba0b2071f43260a9735 /src/mesa/drivers/dri/i965/intel_mipmap_tree.c | |
| parent | 84d27c32d238ca7a7b115bf190e7e527b7f70e92 (diff) | |
i965: Check for miptree pitch alignment before using intel_miptree_map_movntdqa()
We have an assert() in intel_miptree_map_movntdqa() which expects
the pitch to be 16 byte aligned.
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Tapani Pälli <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_mipmap_tree.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 8addcc5010c..593bb9da0d5 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -2630,7 +2630,9 @@ intel_miptree_map(struct brw_context *brw, } else if (use_intel_mipree_map_blit(brw, mt, mode, level, slice)) { intel_miptree_map_blit(brw, mt, map, level, slice); #if defined(USE_SSE41) - } else if (!(mode & GL_MAP_WRITE_BIT) && !mt->compressed && cpu_has_sse4_1) { + } else if (!(mode & GL_MAP_WRITE_BIT) && + !mt->compressed && cpu_has_sse4_1 && + (mt->pitch % 16 == 0)) { intel_miptree_map_movntdqa(brw, mt, map, level, slice); #endif } else { |