From 278460279b4e089d51a24fb01dc56dc1e88dcb72 Mon Sep 17 00:00:00 2001 From: Anuj Phogat Date: Mon, 4 May 2015 23:10:28 -0700 Subject: i965: Check for miptree pitch alignment before using intel_miptree_map_movntdqa() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We have an assert() in intel_miptree_map_movntdqa() which expects the pitch to be 16 byte aligned. Signed-off-by: Anuj Phogat Reviewed-by: Tapani Pälli --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965/intel_mipmap_tree.c') diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 8addcc5010c..593bb9da0d5 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -2630,7 +2630,9 @@ intel_miptree_map(struct brw_context *brw, } else if (use_intel_mipree_map_blit(brw, mt, mode, level, slice)) { intel_miptree_map_blit(brw, mt, map, level, slice); #if defined(USE_SSE41) - } else if (!(mode & GL_MAP_WRITE_BIT) && !mt->compressed && cpu_has_sse4_1) { + } else if (!(mode & GL_MAP_WRITE_BIT) && + !mt->compressed && cpu_has_sse4_1 && + (mt->pitch % 16 == 0)) { intel_miptree_map_movntdqa(brw, mt, map, level, slice); #endif } else { -- cgit v1.2.3