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| author | Jason Ekstrand <[email protected]> | 2020-02-21 13:39:16 -0600 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-02-25 20:12:10 +0000 |
| commit | 5dfd83d7a1ce52a42485c54ca170311449379eb9 (patch) | |
| tree | c32a8db60c3570a1dbc9106025026033269a7837 /src/intel/tools | |
| parent | d4e7a11bc3e33baa311595602719bb449ce51d31 (diff) | |
anv: Always enable the data cache
Because we set the needs_data_cache bit from the NIR during compilation,
any time a shader was pulled out of the pipeline cache, we wouldn't set
the bit and the data cache was disabled. Fortunately, on Gen8+, this
bit is ignored because we always use the ALL section in the L3$ config
instead of separate DC and RO sections. On Gen7, however, this meant
that we were basically never running with the data cache enabled and our
compute performance was suffering massively because of it. This commit
improves Geekbench 5 scores on my Haswell GT3 by roughly 330% (no,
that's not a typo).
Cc: [email protected]
Reviewed-by: Lionel Landwerlin <[email protected]>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3912>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3912>
Diffstat (limited to 'src/intel/tools')
0 files changed, 0 insertions, 0 deletions