diff options
| author | Jason Ekstrand <[email protected]> | 2016-09-12 12:58:38 -0700 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2016-09-14 17:53:16 -0700 |
| commit | 89a96c8f43370cc84adf92ab32e3de302a1fa1d0 (patch) | |
| tree | b5262dfcae89b3be50ceb341d0f8d8aba70c42ec /src/intel/genxml | |
| parent | a814e18c96ccc70473103cf08a675265f0d1b3c9 (diff) | |
anv/cmd_buffer: Set the L3 atomic disable mask bit in CHICKEN3 on HSW
Without this bit set, the value in "L3 Atomic Disable" won't get applied by
the hardware so we won't properly get L3 atomic caching.
Fixes dEQP-VK.spirv_assembly.instruction.compute.opatomic.compex and 198 of
the dEQP-VK.image.atomic_operations.* tests on HSW
Signed-off-by: Jason Ekstrand <[email protected]>
Reviewed-by: Francisco Jerez <[email protected]>
Diffstat (limited to 'src/intel/genxml')
| -rw-r--r-- | src/intel/genxml/gen75.xml | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml index 27112b6fcc2..1debc3ac3e5 100644 --- a/src/intel/genxml/gen75.xml +++ b/src/intel/genxml/gen75.xml @@ -2951,6 +2951,7 @@ <register name="CHICKEN3" length="1" num="0xe49c"> <field name="L3 Atomic Disable" start="6" end="6" type="uint"/> + <field name="L3 Atomic Disable Mask" start="22" end="22" type="uint"/> </register> </genxml> |