From 89a96c8f43370cc84adf92ab32e3de302a1fa1d0 Mon Sep 17 00:00:00 2001
From: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Mon, 12 Sep 2016 12:58:38 -0700
Subject: anv/cmd_buffer: Set the L3 atomic disable mask bit in CHICKEN3 on HSW

Without this bit set, the value in "L3 Atomic Disable" won't get applied by
the hardware so we won't properly get L3 atomic caching.

Fixes dEQP-VK.spirv_assembly.instruction.compute.opatomic.compex and 198 of
the dEQP-VK.image.atomic_operations.* tests on HSW

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
---
 src/intel/genxml/gen75.xml | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/intel/genxml')

diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 27112b6fcc2..1debc3ac3e5 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2951,6 +2951,7 @@
 
   <register name="CHICKEN3" length="1" num="0xe49c">
     <field name="L3 Atomic Disable" start="6" end="6" type="uint"/>
+    <field name="L3 Atomic Disable Mask" start="22" end="22" type="uint"/>
   </register>
 
 </genxml>
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