diff options
author | Jose Maria Casanova Crespo <[email protected]> | 2017-07-01 08:19:17 +0200 |
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committer | Jose Maria Casanova Crespo <[email protected]> | 2017-12-06 08:57:18 +0100 |
commit | c57a3f200dd50e345a9983e5ae950091e6241af6 (patch) | |
tree | 2355bd52109784482d26aebf16cdf7129505c650 /src/intel/compiler/brw_shader.cpp | |
parent | a4031bdfa927fb4c3c5d0bdadc70634f3c1a5eac (diff) |
i965/fs: Add byte scattered read message and fs support
v2: Fix alignment style (Topi Pohjolainen)
(Jason Ekstrand)
- Enable bit_size parameter to scattered messages to enable different
bitsizes byte/word/dword.
- Remove use of brw_send_indirect_scattered_message in favor of
brw_send_indirect_surface_message.
- Move scattered messages to surface messages namespace.
- Assert align1 for scattered messages and assume Gen8+.
- Inline brw_set_dp_byte_scattered_read.
v3: (Jason Ekstrand)
- Use renamed brw_byte_scattered_data_element_from_bit_size method
- Assert scattered read for Gen8+ and Haswell.
- Use conditional expresion at components_read.
- Include comment about params for scattered opcodes.
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_shader.cpp')
-rw-r--r-- | src/intel/compiler/brw_shader.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index 209552e1b29..74b52976d74 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -293,6 +293,10 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op) case SHADER_OPCODE_MEMORY_FENCE: return "memory_fence"; + case SHADER_OPCODE_BYTE_SCATTERED_READ: + return "byte_scattered_read"; + case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: + return "byte_scattered_read_logical"; case SHADER_OPCODE_BYTE_SCATTERED_WRITE: return "byte_scattered_write"; case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL: @@ -999,6 +1003,8 @@ backend_instruction::is_volatile() const case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: case SHADER_OPCODE_TYPED_SURFACE_READ: case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL: + case SHADER_OPCODE_BYTE_SCATTERED_READ: + case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL: case SHADER_OPCODE_URB_READ_SIMD8: case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT: case VEC4_OPCODE_URB_READ: |