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authorRafael Antognolli <[email protected]>2020-02-25 15:08:32 -0800
committerMarge Bot <[email protected]>2020-03-02 22:28:11 +0000
commitb4ddc6139b9534fb4559948ebcbaf96c76097d55 (patch)
tree91443c2a10c428f3899a6b8af75ac86c585f679a /src/gallium
parenta7de6f1321a00316a59effeed93365f6979e6c69 (diff)
iris: Wait for the GPU to be idle before invalidating the aux table.
An end of pipe sync seems to satisfy this restriction. It takes care of GPU hangs seen in dEQP-GLES31.functional.copy_image.* tests. Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4005> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4005>
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/iris/iris_state.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index eac55039ade..3a2d7140c1e 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -5119,6 +5119,18 @@ genX(invalidate_aux_map_state)(struct iris_batch *batch)
return;
uint32_t aux_map_state_num = gen_aux_map_get_state_num(aux_map_ctx);
if (batch->last_aux_map_state != aux_map_state_num) {
+ /* HSD 1209978178: docs say that before programming the aux table:
+ *
+ * "Driver must ensure that the engine is IDLE but ensure it doesn't
+ * add extra flushes in the case it knows that the engine is already
+ * IDLE."
+ *
+ * An end of pipe sync is needed here, otherwise we see GPU hangs in
+ * dEQP-GLES31.functional.copy_image.* tests.
+ */
+ iris_emit_end_of_pipe_sync(batch, "Invalidate aux map table",
+ PIPE_CONTROL_CS_STALL);
+
/* If the aux-map state number increased, then we need to rewrite the
* register. Rewriting the register is used to both set the aux-map
* translation table address, and also to invalidate any previously