diff options
| author | Ilia Mirkin <[email protected]> | 2014-09-01 12:48:12 -0400 |
|---|---|---|
| committer | Ilia Mirkin <[email protected]> | 2014-09-01 18:38:02 -0400 |
| commit | 2528d402b9e35601d4631cd80a301bacd87dfc95 (patch) | |
| tree | 819bbf29079d19f3a055511b2fe558f1b6e7c6f7 /src/gallium | |
| parent | 6c2b079231f84b09b3f35183930afe522baee168 (diff) | |
nv50: set the miptree address when clearing bo's in vp2 init
The mt address is about to be used more, make sure it's set
appropriately.
Reported-by: Emil Velikov <[email protected]>
Tested-by: Emil Velikov <[email protected]>
Signed-off-by: Ilia Mirkin <[email protected]>
Cc: "10.2 10.3" <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/nouveau/nv50/nv84_video.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/gallium/drivers/nouveau/nv50/nv84_video.c b/src/gallium/drivers/nouveau/nv50/nv84_video.c index a39f572f708..b26e1eebfbb 100644 --- a/src/gallium/drivers/nouveau/nv50/nv84_video.c +++ b/src/gallium/drivers/nouveau/nv50/nv84_video.c @@ -482,12 +482,14 @@ nv84_create_decoder(struct pipe_context *context, mip.level[0].pitch = surf.width * 4; mip.base.domain = NOUVEAU_BO_VRAM; mip.base.bo = dec->mbring; + mip.base.address = dec->mbring->offset; context->clear_render_target(context, &surf.base, &color, 0, 0, 64, 4760); surf.offset = dec->vpring->size / 2 - 0x1000; surf.width = 1024; surf.height = 1; mip.level[0].pitch = surf.width * 4; mip.base.bo = dec->vpring; + mip.base.address = dec->vpring->offset; context->clear_render_target(context, &surf.base, &color, 0, 0, 1024, 1); surf.offset = dec->vpring->size - 0x1000; context->clear_render_target(context, &surf.base, &color, 0, 0, 1024, 1); |