From 2528d402b9e35601d4631cd80a301bacd87dfc95 Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Mon, 1 Sep 2014 12:48:12 -0400 Subject: nv50: set the miptree address when clearing bo's in vp2 init The mt address is about to be used more, make sure it's set appropriately. Reported-by: Emil Velikov Tested-by: Emil Velikov Signed-off-by: Ilia Mirkin Cc: "10.2 10.3" --- src/gallium/drivers/nouveau/nv50/nv84_video.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/gallium') diff --git a/src/gallium/drivers/nouveau/nv50/nv84_video.c b/src/gallium/drivers/nouveau/nv50/nv84_video.c index a39f572f708..b26e1eebfbb 100644 --- a/src/gallium/drivers/nouveau/nv50/nv84_video.c +++ b/src/gallium/drivers/nouveau/nv50/nv84_video.c @@ -482,12 +482,14 @@ nv84_create_decoder(struct pipe_context *context, mip.level[0].pitch = surf.width * 4; mip.base.domain = NOUVEAU_BO_VRAM; mip.base.bo = dec->mbring; + mip.base.address = dec->mbring->offset; context->clear_render_target(context, &surf.base, &color, 0, 0, 64, 4760); surf.offset = dec->vpring->size / 2 - 0x1000; surf.width = 1024; surf.height = 1; mip.level[0].pitch = surf.width * 4; mip.base.bo = dec->vpring; + mip.base.address = dec->vpring->offset; context->clear_render_target(context, &surf.base, &color, 0, 0, 1024, 1); surf.offset = dec->vpring->size - 0x1000; context->clear_render_target(context, &surf.base, &color, 0, 0, 1024, 1); -- cgit v1.2.3