diff options
| author | Marek Olšák <[email protected]> | 2018-05-02 18:35:27 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-05-10 18:39:53 -0400 |
| commit | 8b58a14ef76f6d6e6c71fff2cb5c8fa6662a1882 (patch) | |
| tree | c5e0bfbad7d114c929d5f1e5530d0569b0c6bc03 /src/gallium/winsys/radeon | |
| parent | b81149e258a492ed0c81058fb535f6bfdacb36da (diff) | |
ac/gpu_info: add htile_cmask_support_1d_tiling
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/winsys/radeon')
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 6e3162d1cf3..21579fd9563 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -529,6 +529,9 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */ ws->info.ib_start_alignment = 4096; ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40; + /* HTILE is broken with 1D tiling on old kernels and CIK. */ + ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != CIK || + ws->info.drm_minor >= 38; ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL; |